A low power consumption control circuit of ddr controller based on dfi interface

Abstract

The invention discloses a DDR controller low-power control circuit based on a DFI interface. The DDR controller low-power control circuit comprises a DFI parsing module, a programmable gated clock control module and a gated clock generation module. An input end of the DFI parsing module is connected to a DFI output end of DDR control logic in a DDR controller, and an output end of the DFI parsing module is connected to an input end of the programmable gated clock control module. An output end of the programmable gated clock control module is connected to an input end of the gated clock generation module. An output end of the gated clock generation module is connected to a DDR PHY. By parsing a DFI signal which is sent from DDR control logic in the DDR controller to the DDR PHY, several paths of gated clock control signals can be customized according to a programmable gated clock control strategy, so as to realize multiple paths of gated clock output. By classification control and supply of different clocks of logic circuit parts in the DDR PHY, logic state upset rate of the entire circuit is most likely minimized so as to realize dynamic power consumption control.

Description

【Technical field】 [0001] The invention relates to the technical field of dynamic random access memory, in particular to a low power consumption control circuit of a DDR controller based on a DFI interface. 【Background technique】 [0002] see figure 1 As shown, the DDR control logic of the DDR controller is connected to the DDR PHY through the standard DFI interface; when the DDR controller is in the non-sleep mode (or task mode), due to the functional characteristics of the DDR controller, the clock of the DDR PHY does not Can be interrupted, and dynamic power consumption cannot be controlled. 【Content of invention】 [0003] The object of the present invention is to provide a low power consumption control circuit of a DDR controller based on a DFI interface to solve the above technical problems. [0004] In order to achieve the above object, the present invention adopts the following technical solutions: [0005] A low power consumption control circuit of a DDR controll...

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Problems solved by technology

[0002] see figure 1 As shown, the DDR control logic of the DDR controller is connected to the DDR PHY through the standard DFI interface; when the DDR controller is in the non-sleep mode (or task mode), due to the functional characteristics of the DDR controller, the clock of the DDR PHY does not Can be interrupted, dynamic power consumption cannot be controlled

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