Configuration method for exposure units

Abstract

The invention provides a configuration method for exposure units. The configuration method includes steps of: moving the exposure units in the first direction and the second direction perpendicular to a first edge in a certain step length to obtain the number of a first series of effective transistor cores and an exposure unit configuration in the accuracy of the step length; forming a rectangular marking area in edge zones at one side or two sides of a wafer, and configuring the exposure units from an edge of the rectangular marking area close to the center of the wafer to obtain the number of a second series of effective transistor cores and an exposure unit configuration; selecting the exposure unit configuration when the number of the first series of effective transistor cores is the maximum value if the maximum value of the first series of effective transistor cores is greater than that of the second series of effective transistor cores and exceeds a preset limitation of tolerance; and setting an exposure unit with a special size, and exposing a non-exposure area between the marking area and the complete exposure units. According to the configuration method, the utilization of the wafer can be improved considering the demands for maximization of the effective transistor cores and non-exposure of the special area.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a method for arranging exposure units. Background technique [0002] In the semiconductor wafer production process, it is necessary to mark the wafer (lasermark), such as figure 1 As shown, usually above or below the wafer (or both above and below), there should be no graphics in the marking area to avoid the impact of graphics on marking. Therefore, in the photolithography process in the wafer production process, the marking area is usually exposed during the wafer edge exposure (Wafer Edge Exposure, WEE) step, so that the marking leaks out. However, if contact holes and metal vias (Metal Via) are also exposed in a large area, it will cause problems in the planarization of the wafer in local areas, resulting in a decrease in local yield. Therefore, in the levels of contact holes and metal vias The marking area of ​​WEE is not exposed, which requires the exposure...

AI Technical Summary

Problems solved by technology

However, in the existing arrangement, the number of effective dies has not been optimized, e

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