Operation/margin enhancement feature for surface-MEMS structure, and sculpting raised address electrode
A non-planar and planar technology, applied in the process of producing decorative surface effects, microstructure technology, microstructure devices, etc., can solve problems such as structure reduction
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[0027] discussed below Figures 1 to 23 And the various embodiments used to describe the principles of the invention in this patent document are done by way of illustration only and should in no way be construed as limiting the scope of the invention in any way. Those skilled in the art will understand that the principles of the invention may be implemented in any suitable way and in any type of suitably arranged device or system.
[0028] figure 1 is an exploded view of pixel element 10 (shown as a DMD pixel in this example embodiment). Pixel element 10 is one of an array of such pixel elements fabricated on a wafer (substrate) using semiconductor fabrication techniques. The pixel element 10 is a monolithically integrated MEMS superstructure unit fabricated above a SRAM memory unit 11 formed on a wafer. Two sacrificial photoresist layers have been removed by plasma etching to create air gaps between the three metal layers of the superstructure. For the purposes of this il...
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