Erasing method of three-dimensional memory device

A three-dimensional storage and device technology, applied in the field of erasing three-dimensional semiconductor memory devices, can solve problems such as device failure, data retention characteristic degradation, and hole residue, and achieve the effect of avoiding device failure.
CN105575431BActive Publication Date: 2019-10-29INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Patent Information

Authority / Receiving Office
CN Β· China
Current Assignee / Owner
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
Publication Date
2019-10-29

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Abstract

The invention discloses an erasing method for a three-dimensional storage device. The method comprises the steps that 1, an erasing command is received; 2, whether a storage block is selected or not is determined, if yes, the step 3 is performed, and if not, the step 4 is performed; 3, alternate erasing on odd and even word lines is performed, and then the step 5 is performed; 4, all word lines in a storage block which is not selected are floated, and then the method is finished; 5, whether the storage block is successfully erased or not is verified, if yes, the method is finished, and if not, the step 3 is performed. According to the erasing method for the three-dimensional storage device, the odd word lines and the even word lines are alternately gated or floated, a transverse electric field inhibits moving of erasing electron holes, therefore, electrons in a storage layer can be completely erased, no electron hole remains, and a device failure is avoided.
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Description

technical field

[0001] The invention relates to a method for operating a semiconductor device, in particular to a method for erasing a three-dimensional semiconductor storage device. Background technique

[0002] In order to improve the density of memory devices, the industry has made extensive efforts to develop methods of reducing the size of two-dimensionally arranged memory cells. As the size of memory cells in two-dimensional (2D) memory devices continues to shrink, signal collisions and interference can increase significantly, making it difficult to perform multi-level cell (MLC) operations. In order to overcome the limitations of 2D memory devices, the industry has developed memory devices with a three-dimensional (3D) structure to increase integration density by three-dimensionally arranging memory cells on a substrate.

[0003] Such as figure 1 As shown, specifically, a multi-layer stacked structure (for example, a plurality of ONO structures alternating with oxid...

Claims

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