Erasing method of three-dimensional memory device

Abstract

The invention discloses an erasing method for a three-dimensional storage device. The method comprises the steps that 1, an erasing command is received; 2, whether a storage block is selected or not is determined, if yes, the step 3 is performed, and if not, the step 4 is performed; 3, alternate erasing on odd and even word lines is performed, and then the step 5 is performed; 4, all word lines in a storage block which is not selected are floated, and then the method is finished; 5, whether the storage block is successfully erased or not is verified, if yes, the method is finished, and if not, the step 3 is performed. According to the erasing method for the three-dimensional storage device, the odd word lines and the even word lines are alternately gated or floated, a transverse electric field inhibits moving of erasing electron holes, therefore, electrons in a storage layer can be completely erased, no electron hole remains, and a device failure is avoided.

Description

technical field [0001] The invention relates to a method for operating a semiconductor device, in particular to a method for erasing a three-dimensional semiconductor storage device. Background technique [0002] In order to improve the density of memory devices, the industry has made extensive efforts to develop methods of reducing the size of two-dimensionally arranged memory cells. As the size of memory cells in two-dimensional (2D) memory devices continues to shrink, signal collisions and interference can increase significantly, making it difficult to perform multi-level cell (MLC) operations. In order to overcome the limitations of 2D memory devices, the industry has developed memory devices with a three-dimensional (3D) structure to increase integration density by three-dimensionally arranging memory cells on a substrate. [0003] Such as figure 1 As shown, specifically, a multi-layer stacked structure (for example, a plurality of ONO structures alternating with oxid...

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Problems solved by technology

[0006] However, due to the presence of a lateral electric field E' (|E'|<|E|) between the gates of each word line in the selected sub-block, some holes move to the area between two adjacent gate word lines , so that the holes are widely distributed, and there is a mismatch between them and the electrons. After erasing, there are holes remaining on the edge. These residues will cause subsequent data retention characteristics to degrade, and eventually cause device failure.

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