Delay line circuit

Abstract

A delay line circuit is provided and includes a plurality of delay units configured to receive an input signal and to provide a first output signal. The plurality of delay units is configured to selectively invert or relay the input signal to produce the first output signal based on a first instruction received from a delay line controller. A phase interpolator unit includes an offset unit configured to selectively add a speed control unit in the phase interpolator unit based on a second instruction received from the delay line controller. The phase interpolator unit is further configured to receive the first output signal and provide a second output signal. An operating method of the delay line circuit is also provided.

Description

technical field [0001] The present invention relates generally to integrated circuits and, more particularly, to delay circuits. Background technique [0002] Delay elements are the building blocks of clock distribution networks in some integrated circuits and systems. Delay elements are used to define a time base for data movement within these systems. Variable delay elements are inverter-based circuits used for fine, precise, and accurate pulse delay (or phase) control in high-speed digital integrated circuits. In order to achieve a wide delay or phase adjustment, variable delay elements are implemented as inverter chains. The chain of inverters is called a delay line. [0003] In many integrated circuits, delay lines are used in systems such as DLLs (Delay Locked Loops), TDCs (Time-to-Digital Converters), VCOs (Voltage Controlled Oscillators), Pulse Width Controlled Loops (PWCLs), etc. In these applications, variable delay elements are used for precise and accurate pu...

AI Technical Summary

Problems solved by technology

However, in some cases, inconsistent delay step changes increase clock jitter

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