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A method and device for address line fault detection

A fault detection, address line technology, applied in the field of communication, can solve the problem that the address line walking algorithm cannot access the memory address range, cannot detect the address line short circuit, open circuit, fixed logic, etc.

Active Publication Date: 2019-08-06
XINHUASAN INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, in actual implementation, the address line walking algorithm cannot access all memory address ranges, so it is impossible to detect whether the address lines corresponding to the inaccessible memory addresses have faults such as short circuits, open circuits, and fixed logic.

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  • A method and device for address line fault detection
  • A method and device for address line fault detection
  • A method and device for address line fault detection

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Embodiment Construction

[0021] The terminology used in this application is for the purpose of describing specific embodiments only, not to limit the application. As used in this application and the claims, the singular forms "a", "the", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

[0022] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, the information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of the present application, first information may also be called second information, and similarly, second information may also be called first information. Dependi...

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Abstract

The invention provides an address line fault detection method and device.The method comprises the steps of obtaining an initial address corresponding to an address line running algorithm as a base address; according to the initial address, a non-detected address is converted into the base address; whether the current base address is valid or not is judged; if yes, the address line running algorithm is utilized for conducting fault detection on the base address so as to obtain bits and fault bits detected in each detection process; all the fault bits detected in all the detection processes are output.According to the technical scheme, whether a fault exists on a fault line or not can be detected.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a method and device for address line fault detection. Background technique [0002] The CPU (Central Processing Unit, central processing unit) and the memory (that is, the memory stick or memory particles) are connected by lines (such as data lines or address lines), and there may be three types of faults in the lines used to connect the CPU and memory. The three kinds of faults are: 1. Short circuit: the pins of the two lines are shorted together so that the levels of the two lines are the same. If the final level is dominated by the high level, this type of short circuit is called 1. Dominant short circuit, if the final level is dominated by low level, this type of short circuit is called 0 dominant short circuit. 2. Open circuit: some pins with lines are open circuited. 3. Fixed logic: Some pins with lines are fixedly pulled to a fixed level, such as shorted to ground...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/22
CPCG06F11/221
Inventor 刘晓军沈刚
Owner XINHUASAN INFORMATION TECH CO LTD