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A parallel instruction set pre-decoding method and system running on cuda platform

An instruction set and pre-decoding technology, applied in the field of instruction pre-decoding, can solve problems such as unfavorable discovery and positioning, affecting the execution results of the tested software, and limited storage space, so as to improve the efficiency of simulation operation and shorten the debugging operation process , The effect of shortening the time of pre-decoding

Active Publication Date: 2019-01-11
SHENZHEN ACAD OF AEROSPACE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] 1) Most of the current embedded systems adopt the parallel development mode of software and hardware, and the hardware environment is often not available at the beginning of software development. The problem
[0006] 2) It is difficult to implement non-intervention testing for embedded software
But this method leads to code expansion due to the need to modify the software under test
Due to the limited storage space of the embedded system itself, the inserted code may not be able to be loaded; or the real-time performance of the software may deteriorate due to the insertion of the probe code, which may even affect the execution results of the tested software.
[0007] 3) The controllability of the environment is poor
During the test process, it is difficult to save and restore the state and set up specific test scenarios; the test process uses physical time, which makes it difficult to accelerate the test; it is difficult to understand the internal behavior of the system during the test process, which is not conducive to timely discovery and location of the software under test. question
[0008] 4) The versatility of the environment is poor
Many hardware test systems are custom-made and difficult to fit into other projects
[0009] 5) Both the developer's confirmation test and the third-party independent confirmation test require a hardware test environment, which greatly increases the development time and cost, and may cause waste of resources
[0013] Traditionally, the serial algorithm is used. In the instruction registration stage, a large number of memory copies from the host (host) to the device (graphics card device) need to be processed, and the data is more complicated, and the overall efficiency is low.

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  • A parallel instruction set pre-decoding method and system running on cuda platform

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Embodiment Construction

[0042] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

[0043] Such as figure 1 Shown, the present invention runs on the parallel instruction set pre-decoding method of CUDA platform and comprises the following steps:

[0044] S1: Analyze the executable file to obtain binary instructions;

[0045] S2: transfer the obtained binary instruction data and output array into the memory;

[0046] S3: register the binary instruction and the analysis function corresponding to the binary instruction;

[0047] S4: Read binary instructions, and decode all binary instructions in parallel;

[0048] S5: Save the intermediate data after decoding each binary instruction to the corresponding position of the output array;

[0049] S6: Determine whether all the data in the output array have been saved, if yes, send the output array back to the host, if not, continue to step S4;

[0050] S7: After processing by the...

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Abstract

The invention provides a parallel pre-decoding method and system for instruction sets and belongs to the technical field of instruction pre-decoding. The parallel pre-decoding method for the instruction sets comprises the following steps: an executable file is analyzed, and binary instructions are obtained; data of the obtained binary instructions and an output array are transmitted into a memory; the binary instructions and an analytic function corresponding to the binary instructions are registered; the binary instructions are read, and all the binary instructions are subjected to parallel decoding; intermediate data of each binary instruction after decoding are stored in the corresponding position of the output array; whether storage of the data in the output array is all finished is judged, if yes, the output array is sent back to a host end; the output array is displayed after processed by the host end. The parallel pre-decoding method has the beneficial effects that the pre-decoding time of a processor is shortened with increase of the number of the binary instructions, and the simulation running efficiency of an SPARC (scalable processor architecture) and the performance of the processor are improved greatly.

Description

technical field [0001] The invention relates to an instruction pre-decoding technology, in particular to a parallel instruction set pre-decoding method and system running on a CUDA platform. Background technique [0002] As the informatization degree of embedded systems becomes higher and higher, its functions become more and more powerful, and its structures become more and more complex, software has gradually become a key component of embedded systems, and its proportion is increasing. Important and complex functions are realized by software. Whether the critical embedded software can run safely and reliably is directly related to the success or failure of production and scientific research tasks and the safety of personnel. In recent years, there have been more and more cases of major safety accidents caused by software failures at home and abroad. How to ensure the reliability of embedded software, and then ensure the safety and reliability of the entire system has bec...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F9/30
CPCG06F9/30145G06F9/3822
Inventor 吴翔虎项文成陶永超曲明成
Owner SHENZHEN ACAD OF AEROSPACE TECH