Precise timing-sequence reading control circuit used for ultrahigh-speed nonvolatile memory

Abstract

The invention discloses a precise timing-sequence reading control circuit used for an ultrahigh-speed nonvolatile memory. The control circuit comprises a buffer circuit used for buffer amplification of a clock signal so as to improve the load carrying capability of the clock signal; an induction amplifier circuit used for converting information of the memory into digital voltage; an adjustable delay unit used for delaying an input signal before outputting under the control of a delay control signal; a reference pulse generator used for generating reference pulse in each reading period; and a phase discriminator used for carrying out phase comparison on reference pulse and longest delay in a reading path so as to output the delay control signal to the adjustable delay unit. The precise timing-sequence reading control circuit provided by the invention can overcome the problem that timing sequence in the ultrahigh-speed nonvolatile memory is hard to accurately control.

Description

Technical field [0001] The present invention relates to a read timing control circuit, in particular to a precise read timing control circuit for ultra-high-speed non-volatile memory. Background technique [0002] The read timing control circuit used in the ultra-high-speed non-volatile memory in the prior art often adopts the following two methods: the RC delay method and the VT compensation method. Such as figure 1 Shown is a circuit diagram of a conventional read timing control circuit in the prior art. The read timing control circuit includes an RC / VT delay unit, multiple buffers Bclk1, Bclk2, Bufx, Buf0, and multiple sense amplifiers SAx0...Saxn, SA00 ... SA0n, it can be seen from the figure that the entire timing delay is the delay of the delay unit plus the delay from the delay unit to the sense amplifier (the line and logic delay in the figure). [0003] The above-mentioned read timing control circuit has the following disadvantages: [0004] 1) The timing generator (the en...

AI Technical Summary

Problems solved by technology

[0006] In order to overcome the deficiencies in the above-mentioned prior art, the purpose of the present invention is to provide a precise read timing control circuit for ultra-high-speed non-volatile memory, which can solve the problem that the timing in ultra-high-speed non-volatile memory is difficult to precisely control

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