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Synchronous trigger circuit for multi-channel logic analyzer based on calibration

A logic analyzer and trigger circuit technology, applied in the field of logic analyzers, can solve the problems of low identification efficiency of trigger circuits, achieve the effects of correcting channel synchronization deviation, improving accuracy, and improving identification efficiency

Active Publication Date: 2018-11-09
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] Due to the existence of synchronization deviation between channels, in the case of patterns and sequence triggers that require multiple channels to be discriminated at the same time, the recognition efficiency of the trigger circuit shown above is low

Method used

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  • Synchronous trigger circuit for multi-channel logic analyzer based on calibration
  • Synchronous trigger circuit for multi-channel logic analyzer based on calibration
  • Synchronous trigger circuit for multi-channel logic analyzer based on calibration

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Embodiment

[0023] The multi-channel logic analyzer synchronous trigger circuit based on calibration of the present invention, on the basis of the original multi-channel logic analyzer trigger circuit built with several N-channel 1-level code pattern trigger circuits, the N-channel 1-level 1-level The pattern trigger circuit is replaced by an N-channel 1-bit multi-level sequence trigger circuit, and a trigger word conversion module is configured for each N-channel 1-bit multi-level sequence trigger circuit. The trigger word conversion module is based on the synchronization deviation of each channel sent by the calibration circuit Sequence, convert the trigger word originally used in the N-channel 1-bit 1-level pattern trigger circuit into a sequence trigger word to control the triggering of the N-channel 1-bit multi-level sequence trigger circuit to achieve accurate data triggering. Obviously, the N-channel K-level D-bit trigger circuit includes K×D N-channel 1-bit multi-level sequence tri...

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Abstract

The invention discloses a multi-channel logic analyzer trigger synchronization circuit based on calibration, which is constructed by several N-channel 1-bit multi-level sequence trigger circuits, N represents the number of logic analyzer channels, and each N-channel 1-bit multi-level sequence trigger The circuit is equipped with a trigger word conversion module. The trigger word conversion module obtains the N-bit trigger word and the N-channel synchronization deviation sequence, and generates the sequence trigger word of each N-channel 1-bit multi-level sequence trigger circuit to control the N-channel 1-bit multi-level sequence trigger. triggering of the circuit. The invention obtains the sequence trigger words of each channel according to the synchronization deviation, triggers in sequence, can correct the influence of the channel synchronization deviation, improves the identification efficiency of the trigger circuit, and further improves the accuracy of data trigger collection.

Description

technical field [0001] The invention belongs to the technical field of logic analyzers, and more specifically relates to a calibration-based synchronous trigger circuit for multi-channel logic analyzers. Background technique [0002] As a data domain test instrument, a logic analyzer is used for data observation and analysis. After the logic analyzer starts the acquisition process, the data flow is continuously sent to the sampling unit, and then the trigger judgment and data storage are completed. Therefore, the triggering of the logic analyzer not only provides the capture of the data segment that the user cares about, but also the trigger signal itself is also a sign that the logic analyzer will store the data flow that meets the triggering conditions. If the trigger judgment function fails, it will be difficult for the instrument to accurately capture the waveform that needs to be analyzed from the data stream, which will greatly reduce the function of the instrument; a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/20
CPCH03K19/20
Inventor 戴志坚杨万渝严浩褚力
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA