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Time deinterleaving circuit and execution time deinterleaving processing method

A deinterleaving and timing technology, applied in TV, electrical components, standard conversion, etc., can solve problems such as address sequence changes, achieve the effect of reducing the number of reads and writes and improving system performance

Inactive Publication Date: 2016-11-23
MSTAR SEMICON INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Assuming that the bandwidth of the DRAM 132 is quadrupled (the word group becomes 128bits, and 4 units are read and written at a time), although the configuration of the memory remains unchanged (the same is 20×8), the writing / reading address order will change

Method used

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  • Time deinterleaving circuit and execution time deinterleaving processing method
  • Time deinterleaving circuit and execution time deinterleaving processing method
  • Time deinterleaving circuit and execution time deinterleaving processing method

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Embodiment Construction

[0055] The technical terms in the following description refer to the customary terms in this technical field. If some terms are explained or defined in this manual, the explanations of these terms shall be based on the descriptions or definitions in this manual.

[0056] The disclosed content of the present invention includes a time deinterleaving circuit and a time deinterleaving method, which can reduce the times of reading and writing of the memory by the time deinterleaving program. On the premise that implementation is possible, those skilled in the art can select equivalent elements or steps to implement the present invention according to the disclosure in this specification, that is, the implementation of the present invention is not limited to the following embodiments. Since some elements included in the time de-interleaving circuit of the present invention may be known elements individually, on the premise of not affecting the full disclosure and implementability of t...

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Abstract

The invention discloses a time deinterleaving circuit and execution time deinterleaving processing method, which is applied to a communication system and is used for carrying out time deinterleaving processing on an interleaved signal, and the interleaved signal comprises a plurality of units. The time deinterleaving circuit comprises a memory module, used for storing these units, wherein these units form a plurality of unit groups with a plurality of units as unit, and the reading and writing of the memory module uses a unit group as unit; and a temporary memory module, used for temporarily storing the parts of these units to arrange the output sequence of these units.

Description

technical field [0001] The present invention relates to a circuit and method for time deinterleaving, in particular to a circuit and method for time deinterleaving that can reduce the number of accesses to system memory. Background technique [0002] Generally speaking, the broadcast signal of terrestrial digital video broadcasting (digital video broadcasting-Second Generation terrestrial, DVB-T2) will first pass the data through Cell-interleaving (CI) operation and time-interleaving (Time-interleaving, TI) before sending. ) operation to minimize the impact of various interferences on the transmitted data during the transmission process, so that the receiving end can obtain the correct transmitted data. After receiving the signal, the signal receiving end must first go through the Time de-interleaving (Time de-interleaving) operation and Only the Cell de-interleaving operation can correctly decode the data. see figure 1 , which is a functional block diagram of a known sign...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N21/4385H04N21/426H04N7/01
CPCH04N21/43853H04N7/012H04N21/42623
Inventor 王俊杰
Owner MSTAR SEMICON INC