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A jfet tube

An injection area, N-type technology, applied in the field of JFET tubes, can solve problems such as limited withstand voltage, inability to make high-voltage resistant junction field effect transistors, and low device current, and achieve the effect of increasing the withstand voltage

Inactive Publication Date: 2019-06-21
湖州奇奇机电科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Traditional junction field effect transistors withstand voltage through the PN junction, and the way to increase the withstand voltage mainly depends on reducing the concentration of the junction. However, under the current manufacturing process, the degree of withstand voltage is still limited, and it is impossible to make a junction field effect transistor with high voltage resistance, and Reducing the concentration of the junction can easily cause problems such as too small device current and poor stability

Method used

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  • A jfet tube
  • A jfet tube
  • A jfet tube

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0024] Such as figure 1 As shown, the JFET tube of this embodiment includes: a P-type substrate 100, and the P-type substrate 100 is used as a back gate; an N-type implant region 200 is formed in the upper surface layer of the P-type substrate 100; The P-type implanted region 300 formed in the upper surface layer of the N-type implanted region 200, the P-type implanted region 300 is used as a positive gate; the P-type heavily doped region 310 formed in the upper surface layer of the P-type implanted region 300; An N-type heavily doped drain region 210 and a source region 220 are formed at both ends of the upper surface layer of the N-type implant region 200, and the positive gate is close to the source region 220; the drain region 210 and the P-type implant region The first field oxide layer 410 formed on the N-type implant region 200 between 300; the second field oxide layer 420 formed on the N-type implant region 200 between the source region 220 and the P-type implant regio...

no. 2 example

[0027] Such as figure 2 As shown, the difference between this embodiment and the first embodiment is that the P-type doped region 500 is in an "L" shape, and the side close to the P-type implanted region 300 is in contact with the first field oxide layer 410, And it is electrically connected to the positive gate, and both sides of the P-type doped region 500 form a PN junction depletion with the N-type implanted region, so that the P-type doped region 500 with the same volume can achieve better compression resistance, or achieve the same The volume of the P-type doped region 500 required for the anti-pressure effect is smaller, which saves costs;

[0028] In this embodiment, the N-type implant region 200 between the P-type doped region 500 and the first field oxide layer 410 is electrically connected to the drain near the side of the drain region 210, so that the P-type doped region 500 and the first field oxide layer 410 The PN junction formed between the N-type implanted r...

no. 3 example

[0031] Such as image 3 As shown, in this embodiment, compared with the first embodiment, the N-type implanted region 200 is divided into a first N-type implanted region 201 and a second N-type implanted region 202, and the second N-type implanted region 202 is formed on the P-type doped In the upper surface layer of the first N-type implantation region 201 between the impurity region 500 and the P-type implantation region 300, and the multi-substance concentration of the second N-type implantation region 202 is lower than that of the first N-type implantation region 201, increasing the N-type implantation Region 200 surface voltage resistance capability, the depth of the second N-type implant region 202 is greater than the P-type doped region 500 and smaller than the P-type implant region 300, which enhances the depletion withstand voltage capability of the P-type doped region 500, while reducing the impact on the channel The influence of the carrier concentration in the chan...

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Abstract

The invention relates to the technical field of semiconductors, in particular to a JFET, a P-type substrate, an N-type injection region, a P type injection region, a P-type heavily doped drain region and an N-type heavily doped drain region and a source region. A first field oxide layer is located between the drain region and the P-type injection region. A second field oxide layer is located between the source region and the P-type injection region. The P-type doped drain region is formed on the upper of the N-type injection region under the first field oxide layer. A side of the P-type doped drain region near P type injection region is electrically connected with a gate to constitute a second JFET structure. The pinch-off voltage of the second JFET structure is higher than the pinch-off voltage of the JFET structure. The pressure-endurance of the JFET is improved efficiently.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a JFET tube. [0002] technical background [0003] With the rapid evolution of semiconductor technology, such as computers and their peripheral digital products are also being updated day by day. The rapid development of semiconductor technology for the application of integrated circuits for computers and their peripheral digital products is an important factor in the ability to provide high-quality digital products. [0004] Junction field effect transistor (JFET) is one of the most common semiconductor devices, including N-channel junction field effect transistor and P-channel junction field effect transistor. In practical applications, N-channel JFET is commonly used. Due to the small size of the device, the junction field effect transistor has advantages over MOSFETs, which is conducive to the further development of semiconductor devices in the direction of high densi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/808H01L29/06
CPCH01L29/0615H01L29/0684H01L29/808
Inventor 李风浪李舒歆
Owner 湖州奇奇机电科技有限公司