Embedded flash memory and electric current comparison reading circuit thereof

Abstract

The invention discloses an embedded flash memory and an electric current comparison reading circuit thereof. The embedded flash memory comprises: a row decoder, connected to a memory array, and used for, under the control of an input signal, selecting the corresponding row and outputting a word line / word line control signal WL / WLS; the memory array, wherein the intersection of each row of the word line / word line control signal WL / WLS in the memory array and each row bit line corresponds to a memory cell so as to store information, and the intersection of each row of the word line / word line control signal WL / WLS in the memory array in a redundant bit line corresponds to a redundant memory cell so as to match the memory cell current in the read operation and reference capacitive / resistive load at two ends of the current; a column decoder, used for connecting the selected memory cell to the electric current comparison reading circuit in the read operation; and the electric current comparison reading circuit, used for converting the information of the selected memory cell to a digital signal and outputting. The embedded flash memory is capable of obviously improving the read reliability of the flash memory.

Description

technical field [0001] The invention relates to a flash memory and its current comparison readout circuit, in particular to an embedded flash memory (Eflash) using a bandgap reference source and its current comparison readout circuit. Background technique [0002] figure 1 It is a general flash memory structure, including a memory array (Memory array) 101, a row decoder (not shown), a column decoder (CMUX) 102, a current comparator readout circuit (Current comparator) 103, and each row of word lines in the memory array The intersection of WL / WLS and bitline Bitline of each column corresponds to a storage unit bitcell, and the intersection of word line WL / WLS and reference bitline Ref Bitline in each row in the memory array corresponds to a reference storage unit Ref bitcell; [0003] Memory cell circuits such as figure 2 , the circuit includes control tubes NC1, NR1, selection tubes NC2, NR2, the source of the selection tube NC2 is grounded, the source of NR2 is suspended...

AI Technical Summary

Problems solved by technology

[0006] However, Figure 4 The flash memory structure shown has the problem of reference current drift. Currently, in order to solve this problem, a Figure 5 In the circuit shown, a bandgap reference is used to generate a reference current, but the reference current of this structure cannot truly match the influence of the parasitic load on the bit line on the current, and the readout performance varies greatly

[0007] It can be seen that the two types of current comparison readout circuits in the prior art have the problem that the reference current amplitude drifts or the parasitic load does not match, which affects the readout accuracy. Therefore, it is necessary to propose a technical means to solve the above problems

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