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D flip-flop setup time measuring circuit and D flip-flop setup time measuring method

A technology for establishing time and measuring circuits, applied in the direction of measuring electrical variables, measuring electricity, measuring devices, etc., can solve the problem of inaccurate establishment time of D flip-flops

Active Publication Date: 2017-05-31
WUHAN XINXIN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The object of the present invention is to provide a measurement circuit and measurement method of a D flip-flop settling time, to solve the problem of inaccurate settling time of the D flip-flop measured by the existing circuit

Method used

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  • D flip-flop setup time measuring circuit and D flip-flop setup time measuring method
  • D flip-flop setup time measuring circuit and D flip-flop setup time measuring method
  • D flip-flop setup time measuring circuit and D flip-flop setup time measuring method

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Embodiment 1

[0064] The present invention provides a D flip-flop settling time measuring circuit 1, which is used to measure the settling time of the D flip-flop when the output signal flips from low to high. The schematic diagram is as follows image 3 shown. The D flip-flop setup time measurement circuit 1 includes: a first input unit 11 , a first conversion unit 12 and a first output unit 13 .

[0065] Specifically, the first input unit 11 includes two buffers and two delay chains, the two buffers are respectively the first data buffer 111 and the first clock buffer 112, and the two delay chains are The chains are respectively the first data delay chain 113 and the first clock delay chain 114, one end of the first data delay chain 113 is connected with the first data buffer 111, and the first clock delay chain 114 One end of is connected to the first clock buffer 112; specifically, the first data delay chain 113 and the first clock delay chain 114 are delay chains formed by p buffers c...

Embodiment 2

[0071] The present invention provides another measurement circuit 2 of D flip-flop settling time, which is used to measure the settling time of D flip-flop when the output signal is flipped from high to low. The schematic diagram is as follows Figure 4 shown. The D flip-flop setup time measurement circuit 2 includes: a second input unit 21 , a second conversion unit 22 and a second output unit 23 .

[0072] Specifically, the first input unit 11 includes an inverter 211, a second clock buffer 212, and two delay chains, and the two delay chains are respectively the second data delay chain 213 and the second clock delay chain 213. Time chain 214, one end of the second data delay chain 213 is connected to the inverter 211, and one end of the second clock delay chain 214 is connected to the second clock buffer 212; specifically, the Both the second data delay chain 213 and the second clock delay chain 214 are delay chains formed by q buffers connected in series, and q is a non-ze...

Embodiment 3

[0078] A method for measuring the establishment time of a D flip-flop, which is used to measure the establishment time of the D flip-flop when the output signal flips from low to high. The specific flow diagram is as follows Figure 5 shown. The measuring method of described D flip-flop setup time comprises the steps:

[0079] Step S51: when n buffers are added to the first clock delay chain, the output signal of the measurement circuit of the D flip-flop setup time is reversed for the first time;

[0080] Step S52: Adjust the voltage value of the first voltage source to reach the critical state V critical , the output signal of the D flip-flop settling time measurement circuit is not inverted, at V critical When +ΔV, the output signal flips for the first time, and the setup time T of the first D flip-flop is obtained setup1 ,at this time Wherein, ΔV is the adjustable minimum step size of the first voltage source, for the critical state V critical The average delay of ...

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Abstract

The invention provides a D flip-flop setup time measuring circuit and a D flip-flop setup time measuring method. The D flip-flop setup time measuring circuit comprises an input unit, a conversion unit, and an output unit, and further comprises a variable voltage source. By applying a variable voltage to the input unit and adjusting the variable voltage, the delay of a single buffer or a single phase inverter can be changed. In the invention, the setup time of a D flip-flop is no longer associated with the delay of buffers, but associated with the delay difference between buffers caused by the minimum adjustment step size of the voltage. The invention further provides single-buffer and single-phase-inverter average delay measuring circuits and measuring methods. The single-buffer average delay measuring circuit comprises a buffer delay chain and a variable voltage generation circuit, and the single-phase-inverter average delay measuring circuit comprises a phase inverter delay chain and a variable voltage generation circuit. The variable voltage generation circuits apply a variable voltage to the buffer delay chain and the phase inverter delay chain respectively to measure the average delay of a single buffer and the average delay of a single phase inverter at different voltages.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits, in particular to a measurement circuit and a measurement method of a D flip-flop settling time. Background technique [0002] Please refer to figure 1 , which is the schematic diagram of a D flip-flop. Such as figure 1 As shown, the D terminal of the D flip-flop, namely the data input terminal, is connected to the data signal DATA, and the clock input terminal CK is connected to the clock signal CLOCK. When the data signal exceeds the setup time before the rising edge of the clock signal ( figure 1 When the width of the delay between the two dotted lines in ) remains unchanged, the output signal is correct at this time, that is, the value of the data signal when the Q output terminal outputs the rising edge of the clock signal; and when the data signal is at the rising edge of the clock signal When it changes within the width of the setup time before the rising edge,...

Claims

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Application Information

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IPC IPC(8): G01R31/3185
CPCG01R31/318525
Inventor 廖春和何洪楷朱敏
Owner WUHAN XINXIN SEMICON MFG CO LTD
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