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Method for packaging chip into pcb and chip packaging structure

A chip packaging structure and chip packaging technology, applied in semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve the problems of insufficient welding area, gas discharge, etc., and achieve the effect of solving the insufficient welding area

Active Publication Date: 2019-05-07
NEW H3C TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, during the packaging process of existing QFN chips, the solder paste will release certain gases (such as flux volatilization) during the reflow soldering process. outside escape
When the gas cannot escape in time, it will remain at the bottom of the QFN chip to form a large area of ​​voids on the solder joints, resulting in insufficient soldering area

Method used

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  • Method for packaging chip into pcb and chip packaging structure
  • Method for packaging chip into pcb and chip packaging structure
  • Method for packaging chip into pcb and chip packaging structure

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Embodiment Construction

[0037] The present invention will be described in detail below in conjunction with specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, method, or functional changes made by those skilled in the art according to these embodiments are included in the protection scope of the present invention.

[0038] The terminology used in the present invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein and in the appended claims, the singular forms "a", "the", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0039] The present invention divides the holes in the plate into two types of arrays, and throug...

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Abstract

The invention proposes a method for packaging a chip in a printed circuit board (PCB) and a chip package structure. The method comprises the steps of forming a bonding pad on a first surface of a PCB substrate, wherein a plurality of pad holes are formed in the bonding pad, penetrate through the PCB substrate and comprises a first pad hole and a second pad hole; performing hole plug processing on the first pad hole; and printing soldering flux on the bonding pad, surface-mounting a quad flat no-lead (QFN) chip on the soldering flux, and performing reflow soldering on the soldering flux so that the QFN chip is packaged on the bonding pad. The invention designs a new method for packaging the chip in the PCB, new structure characteristic is added into the PCB substrate, so that an enough and effective gas escape path is generated during the package process of the QFN chip, and the problems of insufficient welding area and excessive large hole of an existing QFN chip after reflow welding are solved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for packaging a chip into a PCB and a chip packaging structure. Background technique [0002] QFN is a square flat no-lead package with a square or rectangular appearance. There is a large-area exposed pad at the center of the bottom of the package for heat conduction. The periphery of the package surrounding the large pad is surrounded by conductive pads for electrical connection. [0003] Compared with SOIC (Small Outline Integrated Circuit Package, Small Outline Integrated Circuit Package) and TSOP (Thin Small Outline Package, Thin Small Size Package) packages with traditional airfoil pins, the conduction between the internal pins and pads of the QFN package The path is shortened, the self-inductance coefficient and impedance are reduced, and the overall size of the chip is also significantly reduced, so it is very suitable for applications that require size, w...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/48H01L23/498
Inventor 王雪峰
Owner NEW H3C TECH CO LTD