A method and system for FPGA processing complex matrix multiplication in an LTE receiving system

Abstract

The invention provides a method and a system for processing plural matrix multiplication by an FPGA in an LTE receiving system. The method comprises the steps of receiving MMSE filtering data, wherein the MMSE filtering data comprises a first plural matrix and a second plural matrix which are about to be subjected to multiplication operation; according to the first plural matrix and the second plural matrix, obtaining a first parameter COMM(m,n), a second parameter REAL(m,n) and a third parameter IMAG(m,n); according to the first parameter COMM(m,n), the second parameter REAL(m,n) and the third parameter IMAG(m,n), obtaining a real part Cr(m,n) and an imaginary part Ci(m,n); and according to the real part Cr(m,n) and the imaginary part Ci(m,n), obtaining a third plural matrix, and outputting the third plural matrix. By adopting a serial pipeline architecture, adders are reduced, excessive locating and wiring resources are not wasted, and unification is simple; and matrix multiplication of any series can be established.

Description

technical field [0001] The invention relates to the field of complex matrix multiplication processing in an LTE receiving system, in particular to a method and system for FPGA processing complex matrix multiplication in an LTE receiving system. Background technique [0002] Field programmable gate array FPGA chips are widely used in many fields. FPGA not only contains a series of conventional resources such as logic unit (look-up table / flip-flop), storage unit (BRAM), multiply-add unit (MAC), but also includes Complex calculation units such as DSP and multiplier. With the continuous upgrading of FPGA chips, the functions of FPGA are becoming more and more powerful, so the new FPGA is fully capable of complex calculation work. [0003] In recent years, wireless communication technology has achieved rapid development. From the earliest 1G network to the LTE 4G network that has been put into use today, higher and higher requirements have been put forward for the rapid processi...

AI Technical Summary

Problems solved by technology

[0004] At present, there are generally two ways to realize matrix multiplication based on FPGA: one is to use floating point for calculation, which has high calculation efficiency and complexity, and is inefficient; the other is to use fixed point for calculation. As a fixed point, it can greatly improve the efficiency of calculation

[0005] Through reviewing the literature, it is found that the currently proposed multiplication of fixed-point matrices has backward platforms, complicated control, and inflexible methods, etc., and cannot make good use of FPGA devices to save resources.

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