Correlated Double Sampling Integrator

Abstract

An embodiment of the present invention provides a correlated double-sampling integration circuit, which includes: a sample-and-hold module, an energy storage unit, and a feedback module, the sample-and-hold module is used to sample and hold different input signals, and the energy storage unit uses To store the charge corresponding to the input signal after sampling and holding processing to generate a node signal, the feedback module is used to form a negative feedback loop with the energy storage unit, and then control the node signal in the integration phase and the node signal in the reset phase to be consistent , to avoid the output jump of the correlated double-sampling integration circuit, therefore, the correlated double-sampling integration circuit avoids or weakens the noise caused by the operational amplifier 1 / f noise and mismatch voltage etc. The increase of the correlated double-sampling integrator causes the output jump of the circuit.

Description

technical field [0001] The embodiments of the present invention relate to the field of circuit technology, in particular to a correlated double-sampling integration circuit. Background technique [0002] In order to reduce the influence of 1 / f noise and mismatch voltage of the op amp in the integrating circuit, correlated double sampling technology is usually introduced. Specifically, different input signals are sampled twice, and the input signal after the two sampling Analog subtraction to eliminate noise caused by op amp 1 / f noise and mismatch voltage to obtain true signal levels. [0003] An exemplary correlated double-sampling integration circuit includes: a sampling circuit, an energy storage capacitor and an amplifier. The sampling circuit performs time-division sampling under the control of two-phase non-overlapping clocks Φ1 and Φ2. When the clock Φ1 is high and the clock Φ2 is low, the positive plate of the energy storage capacitor Ci samples the input signal V1, ...

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Problems solved by technology

[0004] However, in the above exemplary correlated double-sampling integration circuit, when the clock Φ1 changes from low to high, the output of the amplifier will jump from the output value of the clock Φ2 to the common-mode voltage Vcm when the clock Φ2 is high; At the high moment, the output of the amplifier will jump from the common-mode voltage Vcm to the sum of the output value and the integral value of the original clock Φ2 stage, which will cause the output jump of the relevant double-sampling integration circuit to increase with the increase of the integration times. bigger

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