Switch chip and method for switch chip

Abstract

A device implementing a scalable low-latency mesh may include a memory management unit, an egress processor, and an egress cell circuit that includes at least a first queue and a second queue. The memory management unit may be configured to buffer first cells for transmission. The egress cell circuit may be configured to queue the first cells from the memory management unit in the first queue, queue second cells from an off-chip memory management unit of another device in the second queue, and schedule the first cells from the first queue and second cells from the second queue for transmission via an egress processor. The egress processor may be configured to transmit the first and second cells over at least one first port.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 293,287, filed February 9, 2016, entitled "Scalable Low Latency Mesh Interconnect for Switch Chips," which is hereby incorporated by reference in its entirety for all purposes. technical field [0003] The present description generally relates to a scalable low-latency mesh comprising a scalable low-latency mesh interconnect for switch chips of a switch device. Background technique [0004] In the enterprise switch market, the bandwidth per switch chip doubles every eighteen months. Due to the increase in bandwidth, power density is also increasing while cost is decreasing. To support the enterprise switch market, effective cooling techniques are required to support the continued development of single-system-on-chip (SoC) implementations. However, an efficient way to scale a system using multiple switch chips may allow for reduced coolin...

AI Technical Summary

Problems solved by technology

However, an efficient way to scale a system using multiple switch chips allows for reduced cooling and / or power requirements

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