A high-speed analog-to-digital conversion device applied in an image sensor
A high-speed analog-to-digital conversion, image sensor technology, applied in image communication, color TV parts, TV system parts and other directions, can solve the problem of analog-to-digital conversion time limit sensor frame rate and other issues
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Embodiment 1
[0041] Such as Figure 4a , Figure 4b , Figure 4c and Figure 4d As shown, the present invention is used to quantize the pixel signal voltage without correlated double sampling (CDS) (the reset signal is not quantized, and CDS quantifies the difference between the pixel reset voltage and the pixel signal voltage). The pixel signal is placed at the input end of the comparator, the ramp signal is placed at the other end of the comparator, and the ramp signal starts from t0 and ends at t4. The comparator toggles at t1. The high-bit count enable is the result of sampling the time between the comparator inversion point t1 and the ramp signal end point t4 by using the falling edge of the high-speed clock. The high-bit count enable and the high-speed clock perform an "AND" operation to obtain a high-bit count pulse. The counter counts the high-order count pulses; the low-order count enable is the result of sampling the time between the comparator inversion point t1 and the end ...
Embodiment 2
[0043] Such as Figure 5a , Figure 5b , Figure 5c and Figure 5d As shown, the difference between this embodiment and Embodiment 1 is that the high-bit count enable is the result of sampling the time between the comparator inversion point t1 and the ramp signal end point t4 by using the rising edge of the high-speed clock, and the low-bit count enables It can be the result of sampling the time between the comparator inversion point t1 and the end point t4 of the ramp signal by using the falling edge of the high-speed clock. The low-bit count pulse occurs within one high-speed clock high level after the comparator flip point. The low-bit counter needs to count down; and the low-bit count pulse occurs within one high-speed clock high level after the ramp signal ends. The low-bit counter needs to be up. count.
Embodiment 3
[0045] Such as Figure 6a , Figure 6b , Figure 6c and Figure 6d As shown, the present invention is used to quantize the pixel signal voltage without correlated double sampling (CDS) (the reset signal is not quantized, and CDS quantifies the difference between the pixel reset voltage and the pixel signal voltage). The pixel signal is placed at the input end of the comparator, the ramp signal is placed at the other end of the comparator, and the ramp signal starts from t0 and ends at t4. The comparator toggles at t1. The high-order count enable is the result of sampling the time between the comparator inversion point t1 and the end point t4 of the ramp signal by using the falling edge of the high-speed clock. The high-order count enable and the high-speed clock perform an "AND" operation to obtain a high-order count pulse; The count enable is the result of sampling the time between the comparator inversion point t1 and the end point t4 of the ramp signal by using the risi...
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