Shift Register

A technology of shift register and potential, which is applied in static memory, digital memory information, instruments, etc., and can solve problems such as misoperation of shift registers

Active Publication Date: 2018-01-02
SHARP KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] If the node N2 is in a floating state when the output signal OUT is at a high level, the potential of the node N2 is changed by the noise attached to the output signal OUT, and the transistor Q2 is turned on, which may malfunction the shift register 900.

Method used

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Effect test

no. 1 approach

[0110]Hereinafter, a shift register according to an embodiment of the present invention will be described with reference to the drawings. In the following description, when the on-terminal of the transistor may be either the source terminal or the drain terminal, the fixed on-terminal of one will be referred to as the source terminal, and the fixed on-terminal of the other will be referred to as the fixed on-terminal of the other. Drain terminal. In addition, a signal input or output via a certain terminal is referred to by the same name as the terminal (for example, a signal input via the clock terminal CKA is referred to as a clock signal CKA). In addition, the potential that turns on the transistor when applied to the gate terminal is referred to as an ON potential, and the potential that turns off the transistor is referred to as an OFF potential. For example, for an N-channel transistor, a high-level potential is an on potential, and a low-level potential is an off poten...

no. 2 approach

[0136] Figure 4 It is a block diagram showing the structure of the shift register which concerns on the 2nd Embodiment of this invention. Figure 4 The illustrated shift register 20 has a configuration in which a function of switching the scanning direction (shift direction) is added to the shift register 10 according to the first embodiment. The shift register 20 includes n unit circuits 11 and n selection circuits 22 . The n unit circuits 11 and the n selection circuits 22 are provided in a one-to-one correspondence. Hereinafter, the selection circuit corresponding to the unit circuit Sri of the i-th stage is referred to as the selection circuit SELi of the i-th stage. The selection circuit 22 has input terminals IN1, IN2, control terminals UD, UDB, and an output terminal Z. The shift register 20 is externally supplied with a start signal ST, two-phase clock signals CK1 and CK2, an initialization signal INIT, and control signals UD and UDB. The control signal UDB is a n...

no. 3 approach

[0143] Image 6 It is a block diagram which shows the structure of the shift register which concerns on the 3rd Embodiment of this invention. Image 6 The illustrated shift register 30 has a configuration in which n unit circuits 31 are connected in multiple stages. The unit circuit 31 has an input terminal IN, clock signals CKA and CKB, an initialization terminal INIT, all-on control terminals AON and AONB, and an output terminal OUT. The shift register 30 is externally supplied with a start signal ST, two-phase clock signals CK1 and CK2, an initialization signal INIT, an all-on control signal AON, and a negative signal AONB of the all-on control signal (hereinafter, simply referred to as a negative signal AONB). ).

[0144] The start signal ST is supplied to the input terminal IN of the unit circuit 31 of the primary stage. The clock signals CK1 and CK2 and the initialization signal INIT are supplied to the n unit circuits 31 in the same manner as the shift register 10 ac...

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Abstract

A transistor Tr8, which has a drain terminal connected to a node N2, a source terminal to which an OFF potential is applied, and a gate terminal connected to an output terminal OUT, is provided in a unit circuit 11 of a shift register to stabilize the potential of the node N2. Furthermore, a transistor Tr9 is provided, which has a drain terminal connected to the output terminal OUT, a source terminal to which the OFF potential is applied, and a gate terminal to which an initialization signal INIT is applied. In this manner, the potential of the node N2 can be controlled at a desired level during initialization regardless of the state of the transistor Tr8 before initialization, and the shift register can be reliably initialized.

Description

technical field [0001] The present invention relates to a shift register, and in particular, is preferably applied to a shift register such as a drive circuit of a display device. Background technique [0002] An active-matrix display device selects pixel circuits arranged two-dimensionally on a row-by-row basis, and displays an image by writing voltages according to image data to the selected pixel circuits. In order to select pixel circuits in units of rows, a shift register that sequentially shifts output signals based on a clock signal is used as a scan line driver circuit. In addition, in a display device that performs dot-sequential driving, a similar shift register is provided inside the data line driving circuit. [0003] In a liquid crystal display device or the like, a driver circuit of the pixel circuit and the pixel circuit are integrally formed using a manufacturing process for forming a TFT (ThinFilm Transistor) in the pixel circuit. In this case, in order to...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C19/28G09G3/20G09G3/36
CPCG09G3/3677G09G3/3688G09G2310/0286G11C7/20G11C19/28G09G2310/08
Inventor 佐佐木宁村上祐一郎古田成山中秀一
Owner SHARP KK
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