Shift Register

A technology of shift register and potential, which is applied in static memory, digital memory information, instruments, etc., and can solve problems such as misoperation of shift registers

Active Publication Date: 2020-05-15
SHARP KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] If the node N2 is in a floating state when the output signal OUT is at a high level, the potential of the node N2 is changed by the noise attached to the output signal OUT, and the transistor Q2 is turned on, which may malfunction the shift register 900.

Method used

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Experimental program
Comparison scheme
Effect test

no. 1 approach

[0111]Hereinafter, a shift register according to an embodiment of the present invention will be described with reference to the drawings. In the following description, when the conduction terminal of a transistor may be a source terminal or a drain terminal, the conduction terminal of one is always referred to as a source terminal, and the conduction terminal of the other is always referred to as a source terminal. drain terminal. In addition, a signal input or output via a certain terminal is called by the same name as the terminal (for example, a signal input via the clock terminal CKA is called a clock signal CKA). In addition, when applied to the gate terminal, the potential that turns on the transistor is called on-potential, and the potential that turns off the transistor is called off-potential. For example, for an N-channel transistor, the high-level potential is the on-potential, and the low-level potential is the off-potential. In addition, the threshold voltage of...

no. 2 approach

[0137] Figure 4 It is a block diagram showing the configuration of the shift register according to the second embodiment of the present invention. Figure 4 The shown shift register 20 is configured by adding a function of switching the scanning direction (shift direction) to the shift register 10 according to the first embodiment. The shift register 20 includes n unit circuits 11 and n selection circuits 22 . The n unit circuits 11 and the n selection circuits 22 are provided in one-to-one correspondence. Hereinafter, the selection circuit corresponding to the unit circuit Sri of the i-th stage is referred to as the selection circuit SELi of the i-th stage. The selection circuit 22 has input terminals IN1, IN2, control terminals UD, UDB, and an output terminal Z. The shift register 20 is externally supplied with a start signal ST, two-phase clock signals CK1 and CK2 , an initialization signal INIT, and control signals UD and UDB. The control signal UDB is a negative (Neg...

no. 3 approach

[0144] Image 6 It is a block diagram showing the configuration of the shift register according to the third embodiment of the present invention. Image 6 The shift register 30 shown has a configuration in which n unit circuits 31 are connected in multiple stages. The unit circuit 31 has an input terminal IN, clock signals CKA, CKB, an initialization terminal INIT, all-on control terminals AON, AONB, and an output terminal OUT. The shift register 30 is externally supplied with a start signal ST, two-phase clock signals CK1, CK2, an initialization signal INIT, an all-on control signal AON, and a negation signal AONB of the all-on control signal (hereinafter referred to as the negation signal AONB for short). ).

[0145] The start signal ST is supplied to the input terminal IN of the primary unit circuit 31 . The clock signals CK1 and CK2 and the initialization signal INIT are supplied to the n unit circuits 31 in the same manner as the shift register 10 according to the firs...

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Abstract

A unit circuit 11 of a shift register is provided with a transistor Tr8 having a drain terminal connected to a node N2, a source terminal to which an off potential is applied, and a gate terminal connected to an output terminal OUT, in order to stabilize a potential of the node N2. The unit circuit 11 is further provided with a transistor Tr9 having a drain terminal connected to the output terminal OUT, a source terminal to which the off potential is applied, and a gate terminal to which an initialization signal INIT is supplied. With this, when performing an initialization, it is possible to control the potential of the node N2 to be a desired level and initialize the shift register certainly, irrespective of a state of the transistor Tr8 before the initialization.

Description

technical field [0001] The present invention relates to a shift register, and in particular, a shift register suitable for use in a drive circuit of a display device or the like is preferable. Background technique [0002] An active matrix display device selects pixel circuits arranged two-dimensionally in units of rows, and writes voltages corresponding to image data to the selected pixel circuits, thereby displaying images. In order to select pixel circuits in units of rows, a shift register that sequentially shifts an output signal based on a clock signal is used as a scanning line driver circuit. In addition, in a display device that performs dot sequential driving, a similar shift register is provided inside the data line driving circuit. [0003] In a liquid crystal display device or the like, a driving circuit of a pixel circuit is integrated with the pixel circuit using a manufacturing process for forming a TFT (Thin Film Transistor: Thin Film Transistor) in the pix...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C19/28G09G3/20G09G3/36
CPCG09G3/3677G09G3/3688G09G2310/0286G11C7/20G11C19/28G09G2310/08
Inventor 佐佐木宁村上祐一郎古田成山中秀一
Owner SHARP KK
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