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Thermally enhanced package to reduce thermal interaction between dies

A technology of heat pipes and heat sinks, which is applied to semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., and can solve problems such as failure, overheating, and insufficient heat transfer of semiconductor devices

Inactive Publication Date: 2018-01-16
GLOBALFOUNDRIES U S INC MALTA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, semiconductor devices are prone to overheating or failure due to insufficient heat transfer

Method used

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  • Thermally enhanced package to reduce thermal interaction between dies
  • Thermally enhanced package to reduce thermal interaction between dies
  • Thermally enhanced package to reduce thermal interaction between dies

Examples

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Embodiment Construction

[0022] In the following description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of exemplary embodiments. It is evident, however, that the exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagrams in order to avoid unnecessarily obscuring illustrative embodiments. Furthermore, unless otherwise indicated, all numbers expressing quantities, ratios and numerical properties of ingredients, reaction states, etc. in this patent specification and claims are to be understood as being modified in all instances by the word "about". .

[0023] The present disclosure addresses and solves the current problem of thermal interaction between IC chips that accompanies forming 2.5D semiconductor packages with memory stacks close to logic chips. According to specific embodiments of the present disclosure, ...

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PUM

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Abstract

The invention relates to a thermally enhanced package to reduce thermal interaction between dies. A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.

Description

technical field [0001] This disclosure relates to the fabrication of semiconductor devices, such as integrated circuits (ICs). The present disclosure is particularly applicable to forming semiconductor packages with chips mounted in close proximity to each other, especially for technology nodes below 14 nanometers (nm). Background technique [0002] In 2.5D packaging, multiple IC chips (eg, logic chips, memory stacks, etc.) are mounted close together to improve performance, bandwidth, and / or functionality. Due to the close proximity of multiple IC chips, these chips are thermally coupled to each other. If one of the IC chips consumes more power than the others, heat may flow from the high power IC chip to the lower power IC chip. Depending on the technology, function, performance and bandwidth, the IC manufacturing technology used for each IC may be different, and thus the junction temperature specification may also be different. Lower power ICs may have lower junction te...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/18H01L23/427H01L21/98
CPCH01L25/0657H01L25/18H01L25/50H01L21/4803H01L21/4871H01L23/04H01L23/3675H01L23/3736H01L23/427H01L24/32H01L24/83H01L2224/16145H01L2224/16225H01L2224/32245H01L2224/73253H01L2225/06513H01L2924/1431H01L2924/1434H01L2924/1436H01L2924/15311
Inventor J·帕特尔S·S·伊耶D·伯杰
Owner GLOBALFOUNDRIES U S INC MALTA