Cross-Coupled Clock Signal Distribution Layout In Multi-Height Sequential Cells For Uni-Directional M1

Abstract

A MOS device includes first, second, third, and fourth interconnects. The first interconnect (402) extends on a first track in a first direction. The first interconnect is configured in a metal layer.The second interconnect (404) extends on the first track in the first direction. The second interconnect is configured in the metal layer. The third interconnect (408) extends on a second track in the first direction. The third interconnect is configured in the metal layer. The second track is parallel to the first track. The third interconnect is coupled to the second interconnect. The second and third interconnects (404. 408) are configured to provide a first signal (Clk). The fourth interconnect (410) extends on the second track in the first direction. The fourth interconnect is configuredin the metal layer. The fourth interconnect is coupled to the first interconnect. The first and fourth interconnects (402, 410) are configured to provide a second signal (Clk) different than the first signal.

Description

[0001] Cross References to Related Applications [0002] This application claims a U.S. patent application entitled "CROSS-COUPLE IN MULTI-HEIGHT SEQUENTIAL CELLS FOR UNI-DIRECTIONAL M1," filed May 27, 2015 No. 14 / 723,357, the entire contents of which are expressly incorporated herein by reference. technical field [0003] The present disclosure generally relates to cross-coupling structures in multi-height sequential cells for unidirectional M1. Background technique [0004] As semiconductor devices are manufactured at smaller sizes, manufacturers of semiconductor devices find it more difficult to integrate greater numbers of devices on a single chip. In addition, modern processing techniques impose more constraints on semiconductor device layout designs, which may result in certain semiconductor layout designs consuming significant areas on metal-oxide-semiconductor (MOS) devices. Therefore, improvements in semiconductor layout design are needed to overcome such limitat...

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Problems solved by technology

[0004] As semiconductor devices are manufactured in smaller sizes, manufacturers of semiconductor devices find it more difficult to integrate larger numbers of devices on a single chip

In addition, modern processing technologies impose more constraints on semiconductor device layout design, which may result in certain semiconductor layout designs consuming significant area on metal-oxide-semiconductor (MOS) devices

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