Matrix calculation instruction and method therefor

Abstract

The invention provides a matrix calculation instruction and a method therefor. The matrix calculation instruction comprises an operation code and an operation domain; the operation code is used for identifying different matrix calculation instructions; and the operation domain is used for indicating data information of the matrix calculation instruction, wherein the data information is a registernumber corresponding to an immediate operand of a specific value or data of a specific size. The matrix data participating in calculation is temporarily stored in a scratch pad memory, so that the data different in width can be supported more flexibly and effectively in a matrix calculation process, and the executive performance of a task containing a large amount of matrix calculations is improved.

Description

technical field [0001] The disclosure relates to a matrix operation instruction and a method thereof, which are used for performing matrix operations according to the matrix operation instruction, and can well solve the problem that more and more algorithms in the current computer field include a large number of matrix operations. Background technique [0002] At present, more and more algorithms in the computer field involve matrix operations. Taking artificial neural network algorithms as an example, various neural network algorithms contain a large number of matrix operations. In the neural network, the operation expression of the output neuron is y=f(wx+b), where w is a matrix, x and b are matrices, and the process of calculating the output matrix y is to multiply the matrix w by the matrix x, and add Matrix b, and then perform an activation function operation on the obtained matrix (that is, perform an activation function operation on each element in the matrix). There...

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Problems solved by technology

[0008] The purpose of this disclosure is to provide a matrix operation device to solve the problems existing in the prior art such as limited inter-chip communication, insufficient on-chip cache, and insufficient flexibility in the supported matrix length.

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