Method and device for reporting and issuing message

Abstract

The invention provides a method for reporting and issuing a message, which includes the following steps: when receiving a message sent by an FPGA, parsing the message header of the message sent by theFPGA; querying for connection interfaces between switching equipment and a CPU in a pre-stored forwarding entry according to the message header information of the message sent by the FPGA; reportingthe message sent by the FPGA to the CPU through the connection interfaces between the switching equipment and the CPU so the CPU can process the message sent by the FPGA; when receiving a processed message issued by the CPU, parsing the message header of the processed message; querying for connection interfaces between the switching equipment and the FPGA in the pre-stored forwarding entry according to the message header information of the processed message; and issuing the processed message to the FPGA through the connection interfaces between the switching equipment and the FPGA.

Description

technical field [0001] The present application relates to the communication field, in particular to a method and device for reporting and sending messages. Background technique [0002] FPGA (Field-Programmable Gate Array, field programmable array) chip is a programmable logic chip, which can realize high-speed business processing capability by writing different program codes. Compared with the processing capability realized by traditional CPU, FPGA Chips have clear advantages. Therefore, current high-performance network devices basically use FPGA chips as the main business processing chips, and CPUs as the control end to implement auxiliary functions. For example, the network protocol message is processed on the CPU, in order to report the network protocol message received by the FPGA chip to the CPU, so that the CPU can process the network protocol message. At present, after the FPGA chip receives the message, it enters the message analysis and query process of the FPGA ...

AI Technical Summary

Problems solved by technology

However, the bandwidth of the PCIE bus between the FPGA chip and the CPU is limited, and the PCIE bus also needs to undertake the channel function for the CPU to issue control commands to the FPGA chip. If there are a large number of messages sent and received between the CPU and the FPGA chip, it will Influence the CPU to issue control instructions to the FPGA chip

On the other hand, the message sent by the FPGA chip to the CPU requires the FPGA to encapsulate a specific message header format for the message so that the CPU can correctly analyze the message, and the CPU sends the message to the FPGA chip. The text encapsulates a specific header format, which increases the development efforts, and cannot be located after a problem occurs

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