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Explicit instruction scheduler state information for the processor

A technology for state information and instruction scheduling, applied in concurrent instruction execution, electrical digital data processing, instrumentation, etc., and can solve problems such as low performance

Active Publication Date: 2021-04-16
MICROSOFT TECH LICENSING LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Alternatively, performance may be lower if the designer chooses an ISA with instructions that consume less power

Method used

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  • Explicit instruction scheduler state information for the processor
  • Explicit instruction scheduler state information for the processor
  • Explicit instruction scheduler state information for the processor

Examples

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Embodiment Construction

[0012] Examples described in this disclosure relate to instruction set architectures (ISAs) and processors that may have instructions organized in groups, such as blocks of instructions, that are fetched, executed, and committed atomically. Thus, a processor can centrally fetch instructions belonging to a single group, map them to execution resources within the processor, execute the instructions, and atomically commit their results. The processor can either commit the results of all instructions, or cancel the execution of the entire group. Instructions within a group can be executed in order of data flow. Additionally, a processor may allow instructions within a group to communicate directly with each other. An instruction that produces a result may, instead of writing the result to a register file, pass the result to another instruction that consumes the result. For example, an instruction to add the values ​​stored in registers R1 and R2 can be expressed as shown in Tabl...

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Abstract

A method is provided that includes fetching a set of instructions, wherein the set of instructions is configured to be executed atomically by a processor. The method also includes, prior to decoding the at least one instruction in the instruction group, scheduling at least one instruction in the instruction group for use by the processing device execution.

Description

Background technique [0001] Designers of instruction set architectures (ISAs) and processors make power and performance tradeoffs. For example, if the designer selects an ISA with instructions that deliver higher performance, the processor's power consumption may be higher. Alternatively, performance may be lower if the designer chooses an ISA with instructions that consume less power. Power consumption may be related to the amount of hardware resources of the processor used by the instructions during execution, such as the arithmetic logic unit (ALU), cache lines or registers. The use of a large number of these hardware resources can deliver higher performance at the expense of higher power consumption. Alternatively, use of a small number of such hardware resources may result in lower power consumption at the expense of lower performance. [0002] Compilers are used to compile high-level code into instructions compatible with the ISA and processor architecture. Compiled ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F8/41
CPCG06F8/41G06F9/38G06F9/3802G06F9/3814G06F9/3836G06F9/3824G06F9/3858
Inventor J·格雷D·伯格A·史密斯
Owner MICROSOFT TECH LICENSING LLC