Method and device for cache replacement

Abstract

The embodiment of the invention provides a cache replacement method and device and relates to the field of data processing technology. The cache replacement method and device are used for increasing the cache hitting rate, so that average cache access delay of a system is lowered. The method can be applied to a system comprising a processor, a cache controller, a cache and a memory, wherein the cache comprises a protection interval and an optimization interval, and data in the protection interval is not replaced. The method comprises the steps that the cache controller receives an access instruction which is sent by the processor and comprises an address of to-be-accessed data; it is determined that the to-be-accessed data is not stored in the cache according to the address of the to-be-accessed data; the cache controller reads the to-be-accessed data from the memory; the cache controller determines a to-be-replaced cache block in the optimization interval; and data in the to-be-replaced cache block is replaced with the to-be-accessed data.

Description

Technical field [0001] The present invention relates to data processing technology, and in particular, to a method and apparatus for cache replacement. Background technique [0002] The system may include a processor, cache, cache controller, memory and memory controller. Wherein the cache can include one or more cache blocks, each cache block is used to store data. After the cache controller receiving the access command sent by the processor, if it is determined to be not stored in the cache data access, i.e. a cache miss, then sends an access instruction to the memory controller, wherein the memory access instruction for instructing the memory controller obtaining data to be accessed and the cache controller sends the data to be accessed. After the cache controller receiving the data to be accessed in the memory controller transmits, to determine if the cache is full, the cache replacement process is performed, specifically: the cached data in the cache block to be replaced is ...

AI Technical Summary

Problems solved by technology

[0004] In the method provided above, D1 is replaced at the first moment. If the data to be accessed at the second moment is D1, the cache controller replaces N1 with D1. In this case, the data in the cache does not include D1, which will lead to The cache hit rate cannot be improved, and the average memory access delay of the system also increases

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