A bit line address selection circuit and non-volatile memory

An address selection circuit and address selection technology, applied in the field of memory, can solve the problems such as the existence of one-level logic delay and the slow speed of bit line precharging, and achieve the effect of improving the speed.

Active Publication Date: 2021-08-17
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Based on this dual-Bank design, the YMUX (bit line address selector) adopts a multi-level design, which needs to have one level dedicated to select which Bank is valid, and the more stages of YMUX, the faster the bit line precharge speed will be. slow
In the process of data comparison and output, it may be necessary to make another selection for the comparison results of the upper and lower Banks, resulting in a first-level logic delay.

Method used

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  • A bit line address selection circuit and non-volatile memory
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  • A bit line address selection circuit and non-volatile memory

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Embodiment Construction

[0034] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

[0035] It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0036] It will be understood that when an element or layer is referred t...

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Abstract

The present invention provides a bit line address selection circuit and a nonvolatile memory, the bit line address selection circuit is used for a nonvolatile memory with at least two memory banks, includes a comparison amplifier, and also includes at least a first bit line address selector and at least a second bit line address selector, wherein the first bit line address selector is connected to the non-inverting input terminal of the comparison amplifier and the first memory bank, and the second bit line address selector is connected to the The inverting input terminal of the comparative amplifier and the second storage bank, the first bit line address selector and the non-inverting input terminal of the comparative amplifier are connected to a reference current through a first switch, the second bit line address selector and The inverting input terminal of the comparison amplifier is connected to the reference current through a second switch. The bit line address selection circuit of the present invention utilizes asymmetric Bank data to offset the asymmetry of the comparison amplifier, thereby canceling the selection level to Bank in the traditional YMUX, and only retaining at least one address decoding selection level to the bit line, which improves the The speed of precharging the bit line, the output result of the comparison amplifier is directly output after being driven and amplified.

Description

technical field [0001] The invention relates to the field of memory, in particular to a bit line address selection circuit and a nonvolatile memory. Background technique [0002] Now, high-speed Flash has become the direction of customer consumption demand. The data reading time of non-volatile memory (NVM) such as Flash usually consists of four parts: address decoding, bit line precharging, cell (bit) current signal amplification, data comparison and output. Among them, the time used for address decoding and data comparison and output accounts for a small proportion of the overall reading time, and the time used for cell current signal amplification is greatly affected by the process, and the space for optimization is limited. Therefore, in the data read time of high-speed Flash, optimizing the speed of bit line precharging is a very important part. [0003] At present, in the design of high-speed Flash, the design method of double Bank (storage body) is usually adopted. ...

Claims

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): G11C16/08G11C16/24
CPCG11C16/08G11C16/24
Inventor王韬
OwnerSEMICON MFG INT (SHANGHAI) CORP