Differential clock tree circuit for high-speed multi-channel interface bus

Abstract

The invention discloses a differential clock tree circuit for a high-speed multi-channel interface bus. The differential clock tree circuit for the high-speed multi-channel interface bus has the characteristics of being low in jitter, simple in structure, capable of being cascaded and high in anti-noise capability, and long-distance transmission of a high-speed clock can be achieved. The highly symmetric full analog differential clock tree circuit of the invention has the characteristics of being low in jitter, simple in structure, capable of being cascaded and high in anti-noise capability, and long-distance transmission of the high-speed clock can be achieved. A cascade circuit formed on the basis of the differential clock tree circuit is of a full differential structure, the differential structure appears in pairs and has strong ability to suppress noises; secondly, the structure adopted by the differential clock tree circuit is a differential input / output structure form, which canrealize cascading; thirdly, a field-effect transistor is used for bias power supply, thus noises on the power supply and ground can be shielded, and the low-jitter characteristics can be realized; andfinally, a collector series resistor of a transistor is adopted to reduce the swing amplitude of a differential signal, the driving capability is high, and long-distance transmission can be realized.

Description

technical field [0001] The invention relates to a high-speed interface bus transmission system, in particular to a differential clock tree circuit for a high-speed multi-channel interface bus. Background technique [0002] In recent years, with the wide application and continuous development of modern high technologies such as wireless communication, satellite positioning, remote control and telemetry technology, and precision guidance, high-speed interface bus chip design technology has become a new hot spot in the semiconductor industry. [0003] In the multi-channel high-speed bus system, the development of the bus is transitioning from the past single-channel high-speed bus to multiple parallel high-speed buses, such as double-rate synchronous dynamic random access memory (DDR) bus, high-speed serial computer expansion (PCIE) bus, The HyperTransport bus is a multi-channel high-speed bus. In fact, a multi-channel bus usually requires a high-speed clock tree as an on-chip ...

AI Technical Summary

Problems solved by technology

However, compared with high-speed interface circuits, the current clock speed is much higher than the ordinary clock frequency, and the clock frequency usually exceeds 1GHz. If this kind of clock tree still uses the traditional clock tree, it cannot meet the requirements of clock drive and jitter characteristics.

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