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Down-sampling circuit and down-sampling method

A down-sampling and circuit technology, applied in the field of down-sampling circuits and down-sampling, can solve the problems of increased calculation amount, waste of storage space by sampling circuits, and difficulty in restoring the overall details of the image, so as to improve the calculation speed and reduce the consumption of memory. Effect

Active Publication Date: 2018-10-02
SHANGHAI ADVANCED RES INST CHINESE ACADEMY OF SCI
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  • Application Information

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Problems solved by technology

[0008] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a down-sampling circuit and a down-sampling method, which are used to solve the waste of storage space of the sampling circuit in the prior art and the increase in the amount of calculation caused by the excessive sampling image. And it is difficult to restore the overall details of the image

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Embodiment 1

[0064] see figure 1 , the present invention provides a down-sampling circuit, the down-sampling circuit includes: a first trigger unit 1, a second trigger unit 2, a third trigger unit 3, a fourth trigger unit 4, a first register 5, a second register 6 , a first comparator 7 , a second comparator 8 , a third comparator 9 and a storage module 10 .

[0065] The first trigger unit 1, the second trigger unit 2, the third trigger unit 3 and the fourth trigger unit 4 respectively receive image data, a bit selection signal and a line selection signal, and are used to output the same sampling Four image data in different rows and columns in the window.

[0066] The input end of the first register 5 is connected to the output end of the first trigger unit 1 for registering the output signal of the first trigger unit 1; the input end of the first comparator 7 is respectively connected to the first A register 5 and the output terminal of the second trigger unit 2 are used to compare the...

Embodiment 2

[0079] The present invention also provides a sampling method, the size of the downsampling window is 2*2, that is, two rows and two columns of four data, the method comprises the following steps:

[0080] Step 1), input image data, select image data in the first row and first column in the downsampling window, and store the image data in the first register.

[0081] As an example, a bit selection signal and a row selection signal are also input while the image data is input, wherein the bit selection signal is 0 to represent the data in the odd columns in the downsampling window, and the bit selection signal is 1 to represent the data in the even columns in the downsampling window; When the line selection signal is 0, it means the data of the odd-numbered lines in the downsampling window, and when the line selection signal is 1, it means the data of the even-numbered lines in the downsampling window.

[0082] Judging the position of the input image data in the downsampling win...

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Abstract

The invention provides a resource-saving down-sampling circuit and a down-sampling method. The problem of complete caching of the input image data stream can be solved by using the position selectionsignal and the row selection signal and a first register and a second register used for temporary storage. The large-scale input image is reduced to a quarter of the size of the original image, and the overall detail features of the original image are not changed in output; the dimension of the input image can be reduced, and only two registers are required in comparison with the mode of using theintermediate storage to store all the data stream input so that memory consumption can be reduced; and the computing speed can be enhanced by the down-sampling method and the down-sampling method canbe implemented in the programmable logic device FPGA. Therefore, the disadvantages in the prior art can be effectively overcome and the industry utilization value is high.

Description

technical field [0001] The invention relates to the technical field of image data sampling circuits, in particular to a down-sampling circuit and a down-sampling method. Background technique [0002] With the improvement of shooting technology, people have higher and higher requirements for high-resolution images. At the same time, with the development of artificial intelligence, image recognition algorithms have also been vigorously developed. When performing a series of calculations in the algorithm on high-resolution images, especially in the convolutional neural network that has a good effect in the field of target recognition, reducing the scale of the calculation results of the middle layer is a very important operation. [0003] In the convolutional neural network, the pooling operation is often encountered, and the pooling layer is often behind the convolutional layer. The feature vector output by the convolutional layer is reduced by pooling, and the overfitting phe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N5/14H04N7/01
CPCH04N5/14H04N7/0102
Inventor 汪辉陈煌田犁封松林
Owner SHANGHAI ADVANCED RES INST CHINESE ACADEMY OF SCI
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