A self-excited variable frequency dynamic burn-in circuit for fpga chips

Abstract

The invention discloses a self-excitation frequency conversion dynamic aging circuit for an FPGA chip, and the aging circuit comprises a first clock self-excitation generation circuit, a second clockself-excitation generation circuit, a junction temperature detection circuit, a clock frequency control circuit and an aging function test circuit. The first clock self-excitation generation circuit is used for generating a clock signal Clk_H with the frequency fH. The second clock self-excitation generating circuit is used for generating a clock signal Clk_L with the frequency fL. The junction temperature detection circuit is used for monitoring a junction temperature state of an FPGA, and outputting an overtemperature alarm signal OT to the clock frequency conversion control circuit. The clock frequency conversion control circuit selects the frequency clock signals Clk_H or CLK_L according to the overtemperature alarm signal OT, and outputs the selected signal to the aging function testcircuit. The function test circuit is used for verifying the functions of FPGA internal logic resources in an aging test environment. According to the actual junction temperature state, the FPGA can automatically adjust the working frequency of the internal logic during dynamic aging, and protects the chip from working under an overtemperature condition.

Description

technical field [0001] The invention relates to the field of burn-in of integrated circuit chips, and more specifically relates to a design of a self-excited variable-frequency dynamic burn-in circuit for a Virtex-7 FPGA chip. Background technique [0002] FPGA (Field Programmable Gate Array, Field Programmable Gate Array) is an integrated circuit that can define hardware functions through software. Dynamic burn-in is an important test item in the reliability screening of integrated circuits, which is used to eliminate early failure products with manufacturing defects. [0003] The existing FPGA dynamic burn-in mainly adopts the method of "providing the burn-in excitation signal by the burn-in equipment, and constructing a BIST (Built-in self-test) burn-in circuit through the internal logic of the FPGA". The basic structure is as follows: figure 1 shown. [0004] In order to ensure the screening effect of FPGA dynamic burn-in, it is generally required to make as many inter...

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Problems solved by technology

[0010] This method generates a high-frequency clock signal through external hardware, and sends it to the FPGA in the high-temperature box through a cable. The disadvantage is that when the cable is long, the attenuation of the signal will be serious and the integrity will be reduced, which will cause FPGA identification errors, especially for Most of Virtex-7 series FPGA products only support 1.8V level, which makes it more difficult to transmit long-distance high-frequency clock signals

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