Multi-value bit weight variable complementor of quantization logic

Abstract

The invention relates to a multi-value bit weight variable complementor of quantization logic. The variable complementor comprises two groups of bit weight input and output terminals and terminal interconnecting lines and is characterized in that the serial numbers of the bit weight input terminals are denoted by f0, f1, f2, f3 and the like; the serial numbers of the bit weight output terminals are denoted by F0, F1, F2, F3 and the like; and the connection mode is that the input terminal f0 is connected with the output terminal F1 and the input terminal f1 is connected with the output terminalF0 under a two-value circumstance, the input terminal f0 is fixedly connected with the output terminal F0 in other multi-value circumstances and the other terminals are connected in the manner of multi-value complementation, for example, the connection of four-value bit weight variable complementation is that the f1 is connected with the F3, the f2 is connected with the F2 and the f3 is connectedwith the F1 and the connection of the five-value bit weight variable complementation is that the f1 is connected with the F4, the f2 is connected with the F3, the f3 is connected with the F2 and thef4 is connected with the F1.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to the realization of one of the basic hardware of multi-valued computer "quantization logic multi-valued bit weight changer" technical background [0002] So far all computers and their related digital systems are binary. Although multi-valued computing has many advantages, it develops very slowly because there is no key hardware supporting multi-valued computing. It can be said that multi-valued computers, especially decimal The realization of the computer is almost zero. In view of this situation, I have proposed a simple and effective multi-valued calculation implementation circuit, especially an effective method for ten-valued calculations and the addition and subtraction of multi-valued, especially ten-valued, implementations with binary hardware. , multiplication, and division arithmetic operations and the key circuits of logic operations, which are called "quantiza...

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Problems solved by technology

[0002] So far all computers and their related digital systems are binary. Although multi-valued computing has many advantages, it develops very slowly because there is no key hardware supporting multi-valued computing. It can be said that multi-valued computers, especially decimal The realization of the computer is almost zero. In view of this situation, I have proposed a simple and effective multi-valued calculation implementation circuit, especially an effective method for ten-valued calculations and the addition and subtraction of multi-valued, especially ten-valued, implementations with binary hardware. , multiplication, and division arithmetic operations and the key circuits of logic operations, which are called "quantization logic" and its circuits. For details, please refer to the patent application (201710023530.1 201710023529.9 201710023528.4 201710024248.5 201710024246.6201710024247.0), the quantization logic mode itself has two kinds of information One is the bit weight information mode, and the other is the width weight information mode. The specific circuits in the two information modes are also quite different. In actual work, the bit weight information and the width weight information are converted to each other. The numerical operation of value information depends on bit weight information, but the performance of natural information is mostly analog information, so obtaining standard bit weight and amplitude weight information will be the key to the actual application of the circuit, and the multi-valued storage method of amplitude weight information is also what we expected

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