Chip semi-automatic synchronization method and system
A synchronization system and semi-automatic technology, applied in the electronic field, can solve problems that affect the synchronization status of the AD9379 chip and the main chip cannot complete the synchronization function, etc.
Active Publication Date: 2018-10-26
SOUTHWEST CHINA RES INST OF ELECTRONICS EQUIP
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However, the synchronization function of the AD9739 chip is limited by the internal delay line of the chip. At a sampling rate of 800MHz to 1100MHz, the main chip cannot complete the synchronization function and enter the synchronization state, which also affects other AD9379 chips entering the synchronization state.
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[0021] All the features disclosed in this specification, or all disclosed methods or steps in the process, except for mutually exclusive features and / or steps, can be combined in any manner.
[0022] Any feature disclosed in this specification, unless specifically stated, can be replaced by other equivalent or equivalent alternative features. That is, unless otherwise stated, each feature is just one example of a series of equivalent or similar features.
[0023] For multiple AD9739 chips to reach the synchronization state, the hardware design must first ensure that the working clock, synchronization clock, and data line sent to the AD9739 chip are designed with equal length; secondly, the AD9739 chip semi-automatic synchronization method is used to configure the master chip and the slave chip.
[0024] The principle block diagram of chip synchronization is as figure 1 As shown, multiple AD9739 chips use the same working clock, and the working clocks are designed with equal length. O...
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The invention discloses a chip semi-automatic synchronization method and system. After a chip is powered up, a master chip MU controller is configured at first, after the MU is locked, a master chip SYCN_OUT is controlled to output 4 phases, each phase is traversed to find a corresponding SYNC_IN effective window, the longest SYNC_IN effective window in the four output phases is found, the outputphase of the master chip SYNC_OUT is configured as a phase corresponding to the longest SYNC_IN effective window, meanwhile the SYNC_OUT output delay is configured as the central position of the effective window, a master chip Rx controller is configured, a lock state is reached, a slave chip MU controller is configured, the configuration parameters are the same as the configuration values of themaster chip MU, a slave chip synchronous controller is configured to work in an automatic slave chip mode, and it is ensured that the synchronous controller reaches a synchronous lock state, a slave chip Rx controller is configured, the lock state is reached. By adoption of the chip semi-automatic synchronization method and system disclosed by the invention, the synchronization problem of an AD9739 chip at a low sampling rate can be effectively solved, and it is ensured that multiple AD9739 chips can be normally synchronized at the sampling rate of 800 MHz to 1100 MHz.
Description
Technical field [0001] The invention relates to the field of electronic technology, in particular to a method and system for chip semi-automatic synchronization. Background technique [0002] The high-speed DAC (Digital To Analog Converter) chip AD9739 introduced by ADI (Analog Devices Inc) has the characteristics of high sampling rate and high resolution. The chip supports multi-chip synchronization function. According to the chip manual, the chip's operating frequency is 800MHz~ 2500MHz, the chip itself has the function of multi-chip synchronization. After power-on, the AD9739 internal registers are configured through the SPI control interface to achieve the synchronization function of multiple AD9739 chips. However, the AD9739 chip's built-in synchronization function is limited by the internal delay line of the chip. The main chip cannot complete the synchronization function at a sampling rate of 800MHz to 1100MHz and enters the synchronization state, which also affects other ...
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Login to View More IPC IPC(8): H04J3/06
CPCH04J3/0685
Inventor 李斌纪小明
Owner SOUTHWEST CHINA RES INST OF ELECTRONICS EQUIP