Integration scheme for gate height control and void free RMG fill
A high-level, cavity technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of device performance degradation, inconsistent gate height of work function materials, short circuits, etc.
Active Publication Date: 2018-11-02
GLOBALFOUNDRIES U S INC MALTA
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Problems solved by technology
Some common issues include high-k damage and loss of work function material (WFM) over the gate fins and inconsistent final gate heights, resulting in varying self-aligned contact (SAC) capping budgets, which can Causes short circuit from S / D to gate electrode, leading to degradation of device performance
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[0020] In the following description, for explanatory purposes, many specific details are set forth to provide a sufficient understanding of the exemplary embodiments. However, it should be clear that these example embodiments can be implemented without these specific details or with equivalent arrangements. In other cases, known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the example embodiments. In addition, unless otherwise indicated, all numbers used in the specification and claims representing the amounts, ratios and numerical attributes of components, reaction conditions, etc., will be understood as being modified in all cases by the term "about".
[0021] The present invention processes and solves the critical dimension (CD) drive metal pinch-off associated with the current traditional work function metal and tungsten (W) deposition, which causes the increase of the gate resistance, the process change of the gate height, and the s...
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The invention relates to the integration scheme for gate height control and void free RMG fill. A method of controlling NFET and PFET gate heights across different gate widths with chamfering and theresulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and ineach cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectricand pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.
Description
Technical field [0001] The present invention relates to the manufacture of semiconductor devices such as integrated circuits (ICs). The present invention is particularly suitable for replacement metal gate (RMG), especially for 10 nanometer (nm) and 7 nanometer technology nodes and below based on fin field-effect transistor (FinFET). Background technique [0002] As the critical dimension (CD) of ICs shrinks, metal filling in the RMG process becomes difficult. The RMG process requires forming a gate opening in the dielectric layer and filling the gate opening with a gate material. As the gate size shrinks, the gate opening may not be fully filled, causing metal pinch off, resulting in high gate resistance. [0003] At present, advanced nodes use a gate work function material (WFM), a filler of gate metal, or one or more recesses of the gate spacer and the dielectric gap filler above the gate to enable The source / drain (S / D) contact is set for the proximity of the process scaling...
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IPC IPC(8): H01L21/8238H01L27/092
CPCH01L21/823821H01L21/823842H01L27/0924H01L29/4966H01L29/517H01L29/66795H01L21/28088
Inventor 苏拉·卡玛·帕特尔大西克典刘佩张志强
Owner GLOBALFOUNDRIES U S INC MALTA