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Soc chip local magnetic shield packaging method and soc chip local magnetic shield package

A packaging method and magnetic shielding technology, which is applied in the field of SoC chip local magnetic shield package and SoC chip local magnetic shield package, can solve the problems of unfavorable cost control and weakened MRAM shielding effect, etc.

Active Publication Date: 2020-02-18
SHANGHAI CIYU INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If magnetic shielding is designed for the entire chip area, the shielding effect on MRAM will be greatly weakened and it will be unfavorable for cost control

Method used

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  • Soc chip local magnetic shield packaging method and soc chip local magnetic shield package
  • Soc chip local magnetic shield packaging method and soc chip local magnetic shield package
  • Soc chip local magnetic shield packaging method and soc chip local magnetic shield package

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Embodiment Construction

[0027] Figure 3 to Figure 6 is a schematic diagram of a SoC chip local magnetic shield packaging method according to a preferred embodiment of the present invention.

[0028] Such as Figure 3 to Figure 6 As shown, the SoC chip local magnetic shield packaging method according to a preferred embodiment of the present invention includes:

[0029] The first step: forming a SoC bare chip 100, wherein an MRAM functional module 10 and a non-MRAM functional module 20 are formed in the SoC bare chip 100;

[0030] Second step: form the first groove 11 on the back side of the SoC bare chip 100, and the first groove region 11 covers the MRAM functional module 10 in the direction from the front to the back side, and the MRAM is formed on the front side of the SoC bare chip 100. A second annular groove 12 is formed around the functional module 10;

[0031] From the front to the back, the first groove 11 does not overlap with the non-MRAM functional module 20 , and the surrounding area ...

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Abstract

The invention discloses a SoC chip local magnetic shielding packaging method and a SoC chip local magnetic shielding package component. The SoC chip local magnetic shielding packaging method of the present invention includes the following steps that: a SoC bare chip is formed, an MRAM function module and a non-MRAM function module are formed in the SoC bare chip; a first groove is formed in the back surface of the SoC bare chip, wherein the region of the first groove covers the MRAM functional module in a direction from a front surface to a back surface, and a second annular groove around theMRAM functional module is formed in the front surface of the SoC bare chip; the first groove is filled with a magnetic shielding material, a magnetic shielding material is formed on the local area ofthe front surface of the SoC bare chip such that the magnetic shielding material completely covers the MRAM functional module and the second annular groove, and the magnetic shielding material does not overlap with the non-MRAM functional module in the direction from the front surface to the back surface; the SoC bare chip with the formed magnetic shielding material is pasted on a pad substrate, so that chip wire bonding is realized, and a chip overall package structure is formed.

Description

technical field [0001] The present invention relates to the magnetic shielding and packaging technology of magnetic random access memory chips, and other magnetic shielding and packaging technologies of magnetic field-sensitive electronic components and related integrated circuit chips, especially a SoC (System on Chip, system-on-chip) A chip local magnetic shield package and an SoC chip local magnetic shield package method. Background technique [0002] Magnetic materials and magnetoresistive elements are widely used in memory and sensor fields. Magnetic memory uses the magnetic moment orientation of the magnetic memory layer to record data, and is a non-volatile storage technology. Magnetic Random Access Memory (MRAM) has both the non-volatility of flash memory and the high-speed read and write capabilities of SRAM, and has energy consumption and high integration in many application scenarios (such as embedded IoT systems) In addition, the erasable and writable times gre...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/31H01L23/552H01L21/56
CPCH01L21/56H01L23/31H01L23/552
Inventor 叶力戴瑾
Owner SHANGHAI CIYU INFORMATION TECH CO LTD
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