A waveform quantization synchronization method of a multi-FPGA multi-channel acquisition system

Abstract

The invention discloses a waveform quantization synchronization method of a multi-FPGA multi-channel acquisition system. Firstly, a reset signal of the first ADC is generated by a DSP, and its hardware is reset, and then the DSP generates an asynchronous reset signal of the next ADC in turn, and then Synchronize the asynchronous reset signal of each ADC to the data synchronous clock domain of the previous ADC through the D flip-flop, generate a synchronous reset signal in the clock domain, and then adjust the input / output delay unit in the FPGA to make the asynchronous reset signal Do not be in the metastable interval under the data synchronization clock domain of the previous ADC, and then reset the ADC through the synchronous reset signal, and finally correct the fixed phase difference between each ADC to complete the waveform quantization synchronization.

Description

technical field [0001] The invention belongs to the technical field of data acquisition, and more specifically relates to a waveform quantization synchronization method of a multi-FPGA multi-channel acquisition system. Background technique [0002] Multi-channel acquisition systems are widely used in various industrial and commercial fields, especially in the field of testing, it is often necessary to obtain the phase relationship of signals between channels, which makes the acquisition system not only have the ability to obtain the signal information of the channel itself, but also obtain the channel correlation information between them. This requires synchronous processing of multi-channel acquisition systems. In the acquisition system after synchronous processing, there is no phase difference between the acquired data after the same signal is input into two channels. [0003] As a real-time processing device, FPGA (Field-Programmable Gate Array) has the characteristics ...

AI Technical Summary

Problems solved by technology

With the continuous development of electronic information technology, various products and projects have higher and higher requirements for the performance of high-speed acquisition systems. The traditional single ADC + single FPGA can no longer meet the index requirements of high-speed acquisition systems, and the sampling rate of single-chip ADCs often cannot To meet the requirements of the acquisition system, building a high-speed acquisition system often requires multiple ADCs to be built together to increase the sampling rate of the entire system. The use of multiple ADCs often leads to insufficient resources inside an FPGA. Due to the current hardware manufacturing level In consideration of cost control, the acquisition system often uses a multi-ADC+multi-FPGA system structure, but this structure brings difficulties to the waveform quantization synchronization of the acquisition system

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