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Proactive error correction failure handling method

A technology of error correction and processing methods, applied in the direction of error detection/correction, electrical digital data processing, generation of response errors, etc., can solve the problem of increasing the number of error bits in stored data, inability to indicate open channel solid state hard disk data migration operations, unknown Read data error rate trends and other issues to achieve the effect of reducing the possibility or frequency

Active Publication Date: 2022-06-14
SILICON MOTION INC (CN)
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Problems solved by technology

However, as the number of memory cell accesses increases, the number of erroneous bits of stored data increases
Since the master device does not know the error rate trend of the read data, it cannot instruct the open channel SSD to perform data migration operations to migrate data to less-used locations

Method used

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Embodiment Construction

[0053] The following will illustrate embodiments of the present invention in conjunction with the relevant drawings. In these drawings, the same designations represent the same or similar elements or method processes.

[0054] It is important to understand that the words "comprising", "including" used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, handling of operations, elements and / or components, but does not exclude the addition of additional technical features, numerical values, method steps, operational processes, elements, assemblies, or any combination of the above.

[0055] The use of words such as "first", "second", "third" and the like in the claims is used to modify the elements in the claims, not to indicate that there is a priority order between them, an antecedent relationship, or one element precedes another element, or the chronological order of the execution of the method steps, only to di...

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Abstract

An embodiment of the present invention proposes a method for handling active error correction failures, including: obtaining completed components from the completed queue; judging whether the execution reply table of the completed components includes an unsafe value, and if so, reassigning the entity address to the corresponding unsafe value and output data write command to submit queue to write the user data to the reallocated physical address, wherein both the completion queue and the submit queue are located in the main device.

Description

Technical field [0001] The present invention relates to flash memory, particularly refers to a flash memory active error correction failure processing method. Background [0002] Flash memory devices are generally divided into NOR flash memory devices and NAND flash memory storage devices. NOR flash memory device is a random access device, the main device (Host) may provide access to any address of the NOR flash memory device on the address pin, and instantly obtain the user data stored on the address from the data pin of the NOR flash memory device. In contrast, NAND flash storage devices are not random access, but sequential access. The NAND flash storage device cannot access any random address like the NOR flash storage device, and the main device instead needs to write the sequence bytes (Bytes) to the NAND flash storage device to define the type of command request (e.g., read, write, erase, etc.), and the address on this command. The address can point to a page (the smallest...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/10
CPCG06F11/1044G06F11/1076G06F11/1048G06F11/102G06F3/0659G06F12/0246G06F11/1068
Inventor 林圣嵂
Owner SILICON MOTION INC (CN)
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