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Margin test for one-time programmable memory (OTPM) array with common mode current source

A technology of current margin and memory, which is applied in the field of margin test of one-time programmable memory array, and can solve problems such as FET oxide damage

Active Publication Date: 2019-04-19
格芯美国公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, multiple programming in OTPM may cause damage to the oxide of the FET

Method used

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  • Margin test for one-time programmable memory (OTPM) array with common mode current source
  • Margin test for one-time programmable memory (OTPM) array with common mode current source
  • Margin test for one-time programmable memory (OTPM) array with common mode current source

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Embodiment Construction

[0011] The present disclosure relates to margin testing, and more particularly, to a circuit and method for margin testing of a one-time programmable memory (OTPM) array with a common-mode current source. In a more specific embodiment, the present disclosure is an improved margin test that tracks the common mode current level of an OTPM cell.

[0012] In a non-volatile cell, the threshold voltage (Vt) shift depends on the charge trapped in the oxide of a pair of field effect transistors (FETs). Programming the FET increases the threshold voltage (Vt), which increases the likelihood of damage to the oxide (ie, the gate of the FET may be shorted to the source). When a fault occurs, the gate is shorted to the source or drain of the FET, depending on the bias conditions. In addition, one-time programmable memory (OTPM) arrays use dual cells and a pair of FETs to program the OTPM array. The dual cell of OTPM is a pair of thin oxide high threshold voltage (HVT) NFET base devices. ...

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Abstract

The present disclosure relates to a structure which includes a current-mirror control node which is configured to adjust a current margin and provide the adjusted current margin to at least one one-time programmable memory (OTPM) cell.

Description

technical field [0001] The present disclosure relates to margin testing, and more particularly, to a circuit and method for margin testing of a One Time Programmable Memory (OTPM) array with a common mode current source. Background technique [0002] One-Time Programmable Memory (OTPM) is programmed by a program operation, followed by a verification test. The stability of the programmed data state is determined by performing a read margin test after programming. Margin testing is used to predict the amount of excess read signal present to compensate for sensing noise, leakage, and other signal detractors. In margin testing, a predetermined sensing imbalance must be overcome to read correct data. If the data fails the margin test, additional programming operations are performed. [0003] The OTPM data cell array is connected to a differential current sense amplifier through true and complementary bit line pairs. The stored data is sensed by sense amplifiers that resolve t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C17/18G11C29/12
CPCG11C17/18G11C29/12G11C29/028G11C29/50G11C29/50004G11C2029/5004G11C2029/5006G11C2029/1204
Inventor J·A·法菲尔德
Owner 格芯美国公司
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