Semiconductor memory device and reset method thereof

Abstract

A semiconductor memory device and a reset method thereof prevent inconsistencies in a busy state between a master side memory chip and a slave side memory chip during a reset operation. A flash memorydevice of the disclosure includes a master side memory chip and at least one slave side memory chip. A controller of the master side memory chip selects the master side memory chip or the slave sidememory chip based on an externally inputted address, and performs a reset of the selected memory chip when a reset command is inputted. The data read from a specific area of a memory cell array of themaster side memory chip is set in a register. The controller controls a readout of the reset in a manner that time required for setting the data of the register is longer than time required for the reset of the selected memory chip.

Description

technical field [0001] The present invention relates to a semiconductor memory device stacked with a plurality of dies or chips and a reset method thereof, and to a device equipped with a serial peripheral interface (SPI) function. Flash memory (flash memory). Background technique [0002] A multichip package is a package formed by stacking multiple dies or chips of the same or different types in one package, for example, by stacking memory chips of the same type to expand storage capacity, or Different storage functions are provided by stacking different kinds of memory chips. For example, in the non-volatile semiconductor memory device of Patent Document 1, a plurality of memory array chips and a control chip for controlling the memory array chips are stacked, and through electrodes of the memory array chip and through electrodes of the control chip are stacked. The electrodes are aligned, and the two through electrodes are electrically connected. In addition, in the se...

AI Technical Summary

Problems solved by technology

[0010] However, in such a single-chip stacked flash memory, the time period when the memory chip on the master side is busy may not match the time period when the memory chip on the slave side is busy.

For example, there is a problem that although the memory chip on the master side is not busy, if the memory chip on the slave side is busy, even if the memory chip on the slave side is selected based on the address from the host computer, the memory chip on the slave side cannot be changed. The chip executes the actions instructed by the host computer

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