Semiconductor storage device and reset method thereof

Abstract

The semiconductor memory device and its reset method of the present invention can prevent the inconsistency of the busy state between the memory chip on the master side and the memory chip on the slave side during the reset operation. The flash memory device of the present invention includes a master-side memory chip and at least one slave-side memory chip. The controller of the memory chip on the master side selects the memory chip on the master side or the memory chip on the slave side based on an address input from the outside, and when a reset command is input, resets the selected memory chip and resets the memory chip on the master side. The data read from a specific area of ​​the chip's memory cell array is set in the register. The controller controls reset reading so that the time required to set the register data is longer than the time required to reset the selected memory chip.

Description

technical field [0001] The present invention relates to a semiconductor storage device with a plurality of dies or chips (chips) stacked and its reset method, and relates to a device equipped with a serial peripheral interface (serial peripheral interface, SPI) function Flash memory (flash memory). Background technique [0002] A multichip package is a package that stacks multiple bare chips or chips of the same type or different types in one package. For example, the storage capacity can be expanded by stacking the same type of memory chips, or Different storage functions are provided by stacking different types of memory chips. For example, in the nonvolatile semiconductor storage device of Patent Document 1, a plurality of memory array chips (memory array chips) and a control chip for controlling the memory array chips are stacked, and the through electrodes of the memory array chips are connected to the through electrodes of the control chips. The electrodes are aligne...

AI Technical Summary

Problems solved by technology

[0010] However, in such a single-chip stacked flash memory, the time period when the memory chip on the master side is busy may not match the time period when the memory chip on the slave side is busy.

For example, there is a problem that although the memory chip on the master side is not busy, if the memory chip on the slave side is busy, even if the memory chip on the slave side is selected based on the address from the host computer, the memory chip on the slave side cannot be changed. The chip executes the actions instructed by the host computer

Images