Compatible with 64b/66b coded pcs sending device and receiving device
A technology of sending device and receiving device, which is applied in the field of receiving device and PCS sending device, and can solve the problem of single PCS codec adaptation function
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Embodiment 1
[0052] In order to solve the problem that the existing FPGA chip internal PCS IP mainly includes 8B / 10B encoding and decoding, and the PCS encoding and decoding function is single, this embodiment provides a PCS sending device based on 64B / 66B encoding, such as figure 1 As shown, the PCS sending device includes a first receiving module 101 , a scrambling module 102 , a first data adaptation module 103 , and a first output module 104 connected in sequence.
[0053] The first receiving module 101 in this embodiment is used to receive input 66-bit coded data, wherein the first receiving module 101 includes a PCS interface, and the PCS interface has a maximum bit width of 34 bits. It can be understood that the 66bit encoded data is the data after 64B / 66B encoding. 64B / 66B encoding encodes 64bit "data or control information" into 66bit blocks for transmission. Among these 66bits, the first two digits represent the synchronization header ( 2bit Sync Header), which is mainly used for...
Embodiment 2
[0061] This embodiment provides a PCS receiving device adapted to 64B / 66B coding, such as Figure 8 As shown, the PCS receiving device adapted to 64B / 66B encoding includes a second receiving module 801 , a movement adjustment judgment module 802 , a data adaptation analysis module 803 , a descrambling module 804 , and a second output module 805 connected in sequence.
[0062] The second receiving module 801 in this embodiment is configured to receive input 66-bit encoded adaptation data. It can be understood that it can receive 66-bit coded adaptation data from the PMA Rx side, and the 66-bit coded adaptation data includes a 2-bit synchronization header and 64-bit coded adaptation data.
[0063] The movement adjustment judging module 802 is used for judging whether to perform bit shift adjustment processing on the 66-bit coded adaptation data. In practical applications, due to the parallel-to-serial conversion of serdes, a bit offset will inevitably occur in the PCS receiving...
Embodiment 3
[0073] This embodiment provides a PCS sending device and a PCS receiving device adapted to 64B / 66B encoding. The existing PCS IP proposes a method for realizing 64B / 66B encoding data adaptation, which has little impact on the original structure of PCS and expands PCS The codec function realizes the support for 64B / 66B at a small cost. Such as Figure 14 As shown, the PCS sending device 1401 is connected to the PMA Tx 1402, and the PCS receiving device 1404 is connected to the PMA Rx 1403. The PCS sending device includes a first input module, a clock compensation module, a scrambling module, a data adaptation module, and an 8B / 10B Coding module; the PCS receiving module includes a second input module, a second data adaptation module (including Word Alignment module, 8B10B decoding, Channel Bonding module, CTC module), mobile adjustment judgment module, data adaptation analysis module, descrambling module , a second clock compensation module, and a second output module.
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