Design method of cascaded FIFO module based on FPGA

Abstract

The invention belongs to the technical field of radar communication, and discloses a design method of a cascaded FIFO module based on an FPGA. The cascade FIFO module comprises a first input first output (FIFO) module and a second FIFO module, the output end of a data acquisition system of the FPGA is connected with the input end of the first FIFO module, the output end of the first FIFO module isconnected with the input end of the second FIFO module, the input end of the first FIFO module is the input end of the cascade FIFO module, and the output end of the second FIFO module is the outputend of the cascade FIFO module. The design method of the cascaded FIFO module based on the FPGA comprises the following steps of establishing a parameter model of the cascaded FIFO module; and respectively calculating the parameters of the first FIFO module and the second FIFO module based on the model. According to the invention, the design constraint of the existing FIFO module core can be solved, a higher input / output bit width ratio is provided to save the system resources.

Description

technical field [0001] The invention relates to the technical field of radar communication, in particular to a design method of an FPGA-based cascaded FIFO module. Background technique [0002] In the signal processing process of the radar system, we usually use the Field Programmable Gate Array (English full name: Field Programmable Gate Array, English abbreviation: FPGA) to store the sampled data, and the FPGA transmits the sampled data to the digital Signal processing (English full name: Digital Signal Processing, English abbreviation: DSP) chip for processing. When the sampled data is transmitted from the FPGA to the DSP chip, the bit width of the data often does not match. At this time, it is necessary to call the FPGA built-in intellectual property (Intellectual Property, IP) core to generate a first-in-first-out (English full name: First Input First) Output, English abbreviation: FIFO module) performs data buffering and then transmits to the digital signal processing...

AI Technical Summary

Problems solved by technology

Due to the high-speed sampling of multi-channel arrays, the bit width of the data sampled by the FPGA will be relatively high. When the sampled data is sent to the DSP, because the DSP only accepts data of 64 bits or less, the FIFO of the existing FPGA The asymmetric bit width ratio range of the module cache data is small and needs to be expanded

However, the existing FIFO modules cannot achieve higher asymmetric bit width ratios ranging from 1:16 to 16:1.

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