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An electrostatic discharge protection structure and method of making the same
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A technology of electrostatic discharge protection and manufacturing method, which is applied to circuits, electrical components, electric solid devices, etc., can solve problems such as inability to achieve uniform conduction and discharge, and achieve the effect of improving the overall protection capability
Active Publication Date: 2020-05-19
YANGTZE MEMORY TECH CO LTD
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[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide an electrostatic discharge protection structure and its manufacturing method, which is used to solve the problem that the electrostatic discharge protection structure in the prior art cannot achieve uniform conduction discharge
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Embodiment 1
[0044] An electrostatic discharge protection structure is provided in this embodiment, please refer to figure 2 , which is shown as a plan layout diagram of the electrostatic discharge protection structure 200, including an idle area 201, a discharge element area 202 and a substrate contact portion 206, wherein the discharge element area 202 surrounds the idle area 201, and the substrate The bottom contact portion 206 surrounds the discharge element region 202 .
[0045] As an example, a plurality of NMOS transistors connected in parallel are arranged in the discharge element region 202 , and the NMOS transistors include a gate 203 , a source 204 and a drain 205 located on both sides of the gate 203 . In this embodiment, at least two of the NMOS transistors share a source, and at least two of the NMOS transistors share a drain, so as to save layout space.
[0046] As an example, a plurality of NMOS transistors may adopt a multi-finger cross-parallel structure (not shown) to ...
Embodiment 2
[0053] This embodiment provides a method for making an electrostatic discharge protection structure, please refer to image 3 , shown as a process flow chart of the manufacturing method, comprising the following steps:
[0054] S1: providing a semiconductor substrate;
[0055] S2: defining an idle area and a discharge element area in the semiconductor substrate, wherein the discharge element area surrounds the idle area;
[0056] S3: forming a plurality of NMOS transistors connected in parallel in the discharge element region;
[0057] S4: forming a substrate contact portion, the substrate contact portion surrounding the area of the discharge element.
[0058] Specifically, the semiconductor substrate may be a P-type substrate, or an N-type substrate provided with a P well.
[0059] Specifically, no discharge element is provided in the idle area. In this embodiment, a step of forming a shallow trench isolation structure in the idle area is also included.
[0060] Specif...
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Abstract
The invention provides an electrostatic discharge protection structure and a manufacturing method thereof. The electrostatic discharge protection structure comprises a free area, a discharge element area and a substrate contact part, wherein the discharge element area surrounds the periphery of the free area and is provided with a plurality of NMOS transistors connected in parallel, and the substrate contact part surrounds the periphery of the discharge element area. The electrostatic discharge protection structure provided by the invention removes the NMOS transistor with the largest centralsubstrate resistance and only retains the surrounding NMOS transistors, and the substrate resistances of the retained NMOS transistors are similar, so that all the NMOS transistors in the electrostatic discharge protection structure can be uniformly conducted and discharged, and the overall protection capability of the electrostatic discharge protection structure is greatly improved.
Description
technical field [0001] The invention belongs to the field of semiconductor integrated circuits, and relates to an electrostatic discharge (Electro-Static discharge, ESD for short) protection structure and a manufacturing method thereof. Background technique [0002] At present, the input and output pads (IO PAD) of high-voltage devices are usually protected by high-voltage NMOS, using a grounded-gate NMOS (Grounded-Gate NMOS, GGNMOS for short) or gate-coupled NMOS (Gate-Couple NMOS, GCNMOS for short) structure. In the existing layout design, the middle of the ESD device is a high-voltage NMOS device, which completely occupies the internal area, and the outside is first connected with a P-type substrate, and the outermost is an N-type guard ring. [0003] The area of ESD devices is usually very large, and now a multi-finger cross-parallel structure (multi-finger) is commonly used. As the number of fingers (usually corresponding to the number of NMOS transistors) increases,...
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