fpga pin bridge short circuit test method

A short-circuit test and pin technology, applied in the field of integrated circuits, can solve the problems of high price of automated test equipment, inability to meet FPGA pins, and limited quantity.

Active Publication Date: 2021-06-18
SHANGHAI ANLOGIC INFOTECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, automated testing equipment has the following problems: on the one hand, automated testing equipment is expensive, which increases the cost of testing; on the other hand, the number of input / output (Input / Output, IO) pipelines of automated testing equipment is limited, which cannot meet the needs of FPGA pins. Demand for large quantities

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Embodiment Construction

[0021] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are part of the present invention Examples, not all examples. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by those skilled in the art to which the present invention belongs. As used herein, "comprising" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, without excluding other el...

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Abstract

The invention provides a pin bridge short-circuit test method of FPGA, comprising constructing a signal excitation module and a signal receiving module through a logic unit of FPGA, the signal excitation module includes m signal excitation units, and the signal receiving module includes m The signal receiving unit, the m is a natural number greater than 0, the signal excitation unit and the signal receiving unit are set in one-to-one correspondence with the pins, and the m said pins are set as the input mode, and the first said signal excitation The unit inputs a moving pulse signal, the access mode of the pin receiving the second signal is set to the output mode, and whenever a new pin is set to the output mode, the signal receiving module collects output signals of the m pins, and then output the m output signals as test results. In the test method, there is no need for additional detection tools, which reduces the cost, and the m pins are tested sequentially without being limited by the number of pins.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an FPGA pin bridge short-circuit testing method. Background technique [0002] Field Programmable Gate Array (Field-Programmable GateArray, FPGA), as a semi-custom circuit in the field of application-specific integrated circuits, not only solves the shortcomings of full-custom circuits, but also overcomes the shortcomings of the limited number of original programmable logic device gates. . [0003] The pins of the FPGA can process and transmit the signals of the FPGA pins to the chip, and can also process the signals output from the chip to the chip pins. In the prior art, automatic test equipment (Automatic Test Equipment, ATE) is often used to Bridge faults between FPGA pins are detected. [0004] However, automated testing equipment has the following problems: on the one hand, automated testing equipment is expensive, which increases the cost of testing; on the o...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/317G01R31/52
CPCG01R31/31715G01R31/2853G01R31/50
Inventor 郑莉袁智皓
Owner SHANGHAI ANLOGIC INFOTECH CO LTD
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