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Unified Error Correction and Error Detection Code Generator
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A technology of error detection codes and code blocks, which is applied in the field of unified error correction and error detection code generators, and can solve the problem of useless protection of information bit blocks
Active Publication Date: 2022-04-05
ALCATEL LUCENT SHANGHAI BELL CO LTD +1
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Therefore, in the view of the inventors, they are useless in protecting information bits
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Embodiment 1
[0133] Such as figure 2 shown in, in this example, with x 3 +x 2 +1 the corresponding CRC generator is used. There are three registers, represented by R1, R2 and R3. There are two XOR operators, denoted by X1 and X2.
[0134] Assumed information bits [b n-1 ,b n-2 ,...,b 2 ,b 1 ,b 0 ] will be processed. Furthermore, the information bits are sent into the CRC generator one by one based on the ascending order of their index.
[0135] In this example, 3 auxiliary bits will be generated. For other numbers of auxiliary bits, a similar approach can be used.
[0136] One scheme to generate 3 auxiliary bits is based on the number of input information bits. When 4, 6 and 8 information bits are respectively input, the auxiliary bits are obtained as the value of the first register R1.
[0137] When 4 information bits b 0 to b 3 is entered, the first register has the value c 0 =b 0 +b 3 , which is the first auxiliary bit.
[0138] When 6 information bits b 0 to b 5 i...
Embodiment 2
[0145] In this example, image 3 The CCITT CRC-16 generator shown in is used. It includes 16 registers represented by R0-R15 and three XOR operators.
[0146] information bits [b n-1 ,b n-2 ,...,b 2 ,b 1 ,b 0 ] will be processed. The information bits are sent into the CRC generator one by one based on the ascending order of their index.
[0147] The 16 CRC bits are obtained by fetching the register value when all n information bits are input into the generator. In this embodiment, the number of auxiliary bits J'=4. When 18, 19, 20, 21 information bits are respectively input into the CRC generator, the auxiliary bit is obtained by fetching the value of the register R5. Then, the four auxiliary bits are:
[0148] c 0 =b 1 +b 17 +b 12
[0149] c 1 =b 2 +b 18 +b 13
[0150] c 2 =b 3 +b 19 +b 14
[0151] c 3 =b 4 +b 20 +b 15
[0152] In this embodiment, the auxiliary bits are transmitted after permutation so that they follow their corresponding informa...
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Abstract
A method is provided, the method comprising: if K information bits are sequentially input into a generating part comprising J registers, generating J additional bits; at least one of the K information bits has been input After entering the generating part, and before the K information bits are input into the generating part, fetch J* additional bits from J registers; construction consists of K information bits, J additional bits, and J* additional bits A code block of each bit in , wherein each of the K information bits, J additional bits, and J* additional bits is at a corresponding predetermined position of the code block; polar encoding is performed on the code block.
Description
technical field [0001] The present invention relates to devices, methods and computer program products related to error detection. [0002] abbreviation [0003] 3GPP 3rd Generation Partnership Project [0004] 5G 5th generation [0005] BLER block error rate [0006] CRC Cyclic Redundancy Check [0007] DCI Downlink Control Information [0008] DL downlink [0009] eMBB Enhanced Mobile Broadband [0010] FAR false positive rate [0011] mMTC Massive MTC [0012] MTC Machine Type Communications [0013] PC polar coding [0014] RAN radio access network [0015] RRC Radio Resource Control [0016] TX transmit / transmit [0017] UCI Uplink Control Information [0018] UL uplink [0019] XOR exclusive or Background technique [0020] The polar code proposed in [1] was decided to be used for 5G eMBB control channel and possibly also for mMTC because it has some advantages compared to other candidate coding schemes, e.g., low complexity, capacity realization. [0...
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