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Interrupt delay counting system and method based on FPGA

A counting method and counter technology, which is applied in the computer field, can solve the problems that there is no processing method, and the module that sends the interrupt cannot directly know the length and time required for the host to process the interrupt, so as to achieve strong applicability, portability and enhanced reusability , the effect of highlighting the substantive characteristics

Active Publication Date: 2020-02-07
INSPUR SUZHOU INTELLIGENT TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In terms of hardware logic, there is no general approach
[0005] However, the results calculated by software are not as accurate as those obtained by hardware logic calculations, and the module that sends the interrupt cannot directly know the length of time the host processes the interrupt. The host needs to inform the module of the calculated result by writing the register, and the configuration register is also takes time, which in turn leads to new delays

Method used

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  • Interrupt delay counting system and method based on FPGA
  • Interrupt delay counting system and method based on FPGA

Examples

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Embodiment Construction

[0032] Specific embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0033] Such as figure 1 As shown, the present invention provides a FPGA-based interrupt delay counting system, including a host and 32 peripherals, the peripherals respectively send interrupt request signals to the host, and also include an interrupt delay counter, the interrupt delay The counters are connected to the host and peripherals respectively. The interrupt delay counter includes: a configuration module, a control module and a counting module, the configuration module and the control module are respectively connected to the counting module, the configuration module, the control module and the counting module are respectively connected to the host computer, and the counting module is connected to the peripherals. The counting module includes 32 counting units, and each counting unit is respectively connected to a peripheral for receiving an int...

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PUM

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Abstract

According to the FPGA-based interrupt delay counting system and a method provided by the invention, the interrupt delay counter can accurately calculate the interrupt processing duration of the host from peripheral interrupt triggering to interrupt service program processing completion of the host. A calculation result does not need to inform the corresponding interrupt module through a host, andthe interrupt module can directly obtain the corresponding duration from the delay counter.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to an FPGA-based interruption delay counting system and method. Background technique [0002] With the increasingly widespread application of heterogeneous acceleration, FPGA-based accelerator cards are also developing rapidly. The accelerator card FPGA is connected to the server host through the PCIE interface, and the server host sends the data to be accelerated to the accelerator card FPGA through the PCIE interface, and the accelerator card FPGA returns relevant data through the PCIE interface after processing. [0003] Throughout the system, there are many peripherals that need to send interrupts to the host, and the host executes the interrupt service routine to handle the interrupts. The interrupts of some devices are delay-sensitive. In some specific applications, it is necessary to know the length of time the host processes the interrupts, which requires calculat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/24G06F13/42
CPCG06F13/24G06F13/4282
Inventor 王峰
Owner INSPUR SUZHOU INTELLIGENT TECH CO LTD
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