Method, device and equipment for acquiring running state information of voltage inverter chip
A technology of operating status information and voltage inverters, which is applied in instruments, electrical digital data processing, hardware monitoring, etc., can solve problems such as difficult operation methods, damage to motherboard and BMC particles, and high risks, so as to reduce risks and reduce development capabilities The effect of high requirements and simplified operation process
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Embodiment 1
[0048] see figure 2 , figure 2 It is an implementation flow chart of a method for obtaining operating state information of a voltage inverter chip in an embodiment of the present invention, and the method may include the following steps:
[0049] S201: Obtain a level state transition indication signal.
[0050] It can be set in advance to control the working state of the baseboard management controller through the level state, and obtain the level state transition indication signal in real time or at regular time intervals.
[0051] S202: Determine whether the level state transition indication signal is an enable signal, if yes, perform step S203, and if not, perform step S204.
[0052] You can pre-set the high level as the enabled state of the baseboard management controller, and the low level as the disabled state of the baseboard management controller; or set the low level as the enabled state of the baseboard management controller, and the high level as the baseboard m...
Embodiment 2
[0060] see image 3 , image 3 It is another implementation flow chart of the method for obtaining the operating state information of the voltage inverter chip in the embodiment of the present invention, and the method may include the following steps:
[0061] S301: Obtain a level state transition indication signal input through the complex programmable logic device.
[0062] Such as Figure 4 , Figure 5 , Figure 6 As shown, three pin pins can be set on the main board, the pin output level can be selected with a jumper cap, and a complex programmable logic device CPLD can be set between the pins and the baseboard management controller, and the programmable The GPIO1 interface of the logic device is connected to the No. 2 pin of the pin, and the GPIO2 interface of the programmable logic device is connected to the base board management controller. The number pin is grounded. A level state transition indication signal incoming through a complex programmable logic device c...
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