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Dual-channel shared clock trigger delay adjusting device based on PCI bus

A PCI bus, dual-channel technology, applied in the field of dual-channel shared clock trigger delay adjustment devices, can solve the problems of different delay times and errors that cannot be ignored, and achieve the effects of high measurement synchronization accuracy and high delay accuracy

Active Publication Date: 2020-04-03
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the instrument also has a delay from triggering to actual acquisition, and the delay time of different instruments is different. In the case of high synchronization accuracy requirements, the error caused by the delay cannot be ignored

Method used

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  • Dual-channel shared clock trigger delay adjusting device based on PCI bus
  • Dual-channel shared clock trigger delay adjusting device based on PCI bus
  • Dual-channel shared clock trigger delay adjusting device based on PCI bus

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0033] figure 1 It is a structure diagram of a specific embodiment of a PCI bus-based dual-channel shared clock trigger delay adjustment device of the present invention.

[0034] In this example, if figure 1 As shown, a dual-channel shared clock trigger delay adjustment device based on the PCI bus of the present invention includes: a PCI bus, a power supply module, a signal input interface, a signal output interface, and a delay adjustment control module. system of measurement;

[0035] PCI bus, used to transmit the delay parameters of the control equipment to the device, and supply power to each module in the device;

[0036] The power supply module supplies power to the whole device through the PCI bus;

[0037] The PCI bus needs to provide 3.3V, 5V, ±12V power supply for each module, so the power supply module needs to provide 3.3V, 2.5V and 1.2V power supply input. Compared with 2.5V and 1.2V power supply, this embodiment adopts two LDO power supply chips of Linear Tec...

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Abstract

The invention discloses a dual-channel shared clock trigger delay adjustment device based on a PCI bus. The method comprises the following steps: firstly, a clock signal and a trigger signal are provided for a delay adjustment control module through an external clock and a trigger source via a signal input interface; meanwhile, control equipment sends a delay adjustment parameter to the delay adjustment control module through a PCI bus; the delay adjustment parameter is input to a parameter analysis module through a PCI interface of the delay adjustment control module, and finally delay adjustment is performed on the clock signal and the trigger signal according to an analysis value so as to compensate the problem of measurement asynchronization caused by self delay of a measurement system, and thus the measurement synchronization precision of the measurement system is enabled to be higher.

Description

technical field [0001] The invention belongs to the technical field of synchronous measurement, and more specifically relates to a PCI bus-based dual-channel shared clock trigger delay adjustment device. Background technique [0002] Measurement is a means for human beings to understand the unknown world, and measurement data is the source of information for people to judge things. In some measurement fields, there are extremely high precision requirements for the consistency of measurement time, that is, simultaneous measurement of multiple or multiple devices is required. Synchronous measurement is conducive to improving the measurement accuracy and realizing multi-directional measurement of transient signals. It is widely used in transient signal monitoring and emission source location. [0003] There are many commonly used multi-device synchronization measurement methods, the most representative ones are the measurement method of master control command, the measurement ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05B19/042
CPCG05B19/0423G05B2219/24215Y02D10/00
Inventor 师奕兵张伟李焱骏顾正华张文清周健王轶人郭一多罗欣怡
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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