A Distributed Shared Clock Triggered Delay System

A distributed clock technology, applied in time division multiplexing systems, electrical components, multiplexing communications, etc., can solve problems such as different delay times, errors that cannot be ignored, and large error gaps, and achieve high measurement synchronization accuracy. , the effect of high delay precision

Active Publication Date: 2021-03-30
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the instrument also has a delay from triggering to actual acquisition, and the delay time of different instruments is different. In the case of high synchronization accuracy requirements, the error caused by the delay cannot be ignored
Especially in the synchronization of long-distance multi-measurement systems, the error is even more disparate

Method used

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  • A Distributed Shared Clock Triggered Delay System
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  • A Distributed Shared Clock Triggered Delay System

Examples

Experimental program
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Embodiment

[0048] figure 1 It is a structure diagram of a specific implementation mode of a distributed shared clock trigger delay adjustment system of the present invention.

[0049] In this example, if figure 1 As shown, a distributed shared clock trigger delay adjustment system of the present invention includes: a main control device, a plurality of dual-channel shared clock trigger delay adjustment devices, and a master control device connected to multiple dual-channel shared clock trigger delay adjustment devices local area network;

[0050] Among them, such as figure 2 As shown, the dual-channel shared clock trigger delay adjustment device includes the following components:

[0051] The PCI bus is used to realize the data transmission between the master control device and the dual-channel shared clock trigger delay adjustment device, and to supply power to each module in the device;

[0052] The power supply module supplies power to the whole device through the PCI bus;

[00...

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Abstract

The invention discloses a distributed shared clock trigger delay adjustment system. First, through the main control device through the local area network, the RJ-45 interface sends control messages to each dual-channel shared clock trigger delay adjustment device respectively, and then analyzes the timing time and Adjust the delay parameters, and send the delay adjustment parameters to the delay adjustment control module through the PCI bus; each dual-channel shared clock triggers the delay adjustment device to broadcast its own PTP synchronization message to the LAN through the RJ-45 interface, thereby realizing clock synchronization and obtaining PTP Synchronize the clock; then after the PTP synchronous clock reaches its respective timing time, the CPU sends a start signal to the FPGA, and adjusts the delay of the clock signal and the trigger signal based on the PTP synchronous clock, so as to compensate the measurement error caused by the system's own delay. Synchronization problems, so that the measurement synchronization accuracy is higher.

Description

technical field [0001] The invention belongs to the technical field of synchronous measurement, and more specifically relates to a distributed shared clock trigger delay adjustment system. Background technique [0002] Measurement is a means for human beings to understand the unknown world, and measurement data is the source of information for people to judge things. In some measurement fields, there are extremely high precision requirements for the consistency of measurement time, that is, simultaneous measurement of multiple or multiple devices is required. Synchronous measurement is conducive to improving the measurement accuracy and realizing multi-directional measurement of transient signals. It is widely used in transient signal monitoring and emission source location. [0003] There are many commonly used multi-device synchronization measurement methods, the most representative ones are the measurement method of master control command, the measurement method of unifi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/06
CPCH04J3/0667H04J3/0682
Inventor 张伟顾正华李焱骏张文清师奕兵周健张静王轶人罗欣怡郭一多
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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