Method and system for testing system-on-chip chip

Abstract

The invention discloses a method and a system for testing a system-on-chip chip. The method comprises the following steps: diagnosing and calibrating a first adapter and a second adapter which are connected based on a high-speed serial link; after the diagnosis and calibration are completed, obtaining test excitation vectors and expected vectors of to-be-tested system-on-chip chips one by one through the first adapter, compressing and packaging the test excitation vectors based on the high-speed serial link, and transmitting the compressed and packaged test excitation vectors to the second adapter to obtain a test excitation vector of a certain to-be-tested system-on-chip chip; and verifying the obtained test excitation vector, and if the vector passes verification, correspondingly transmitting the test excitation vector to the input pin of the corresponding to-be-tested system-on-chip chip so as to complete the test. According to the method, a traditional test cable is replaced by a high-speed serial transmission medium, a test excitation vector is serialized and then compressed and added to a verification mechanism, so that mapping from the test excitation vector to an input pinof a to-be-tested system-on-chip chip is completely programmable, and the accuracy of a test result is guaranteed.

Description

technical field [0001] The invention relates to a testing method for a system-on-chip chip, and also relates to a corresponding testing system for a system-on-chip chip, belonging to the technical field of integrated circuit testing. Background technique [0002] In recent years, with the development of mobile Internet, SoC has been widely used. From the perspective of the application requirements and development characteristics of the system-on-chip, the system-on-chip is not like a traditional integrated circuit. It is no longer a circuit with a single function. Analog circuits are precisely integrated. Especially with the expansion of the application field of the SoC chip, more functions, higher integration and faster speed will be integrated in the SoC chip; therefore, there are some new requirements for SoC chip testing, such as : How to meet the ever-increasing and changing test functions of SoCs; how to solve the increase in test costs caused by the expansion of aut...

AI Technical Summary

Problems solved by technology

However, due to the large number of pins on the SoC, signal integrity issues such as signal interference between cables become the main reason for limiting the test frequency.

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