A high speed parallel data receiving system based on clock driver and fpga

Abstract

The invention discloses a high-speed parallel data receiving system based on a clock driver and an FPGA. The high-speed parallel data receiving system comprises the clock driver, the FPGA and a radiofrequency ADC. Wherein the quantized data output of the radio frequency ADC is parallel LVDS; an ADC output associated clock is divided into two (not less than 2) through the clock driver 1. Each pathof independent clock signal passing through the clock driver and each group of data signals of the high-speed ADC are uniformly input into the same BANK of the FPGA, and high-speed parallel data receiving is realized by utilizing an Iserdes (input serial-parallel converter) element in the FPGA. According to the high-speed parallel data receiving system, the clock driver is introduced to create apseudo clock and the Iserdes (input serial-to-parallel converters) primitives in the FPGA are utilized, so that the difficulties encountered by high-speed parallel data receiving of the FPGA are solved.

Description

technical field [0001] The invention relates to the technical field of full waveform acquisition of laser radar echo signals, in particular to a high-speed parallel data receiving system based on a clock driver and FPGA. Background technique [0002] Lidar is an active remote sensing detection technology. The pulse width of laser emission is at the ns level, while the echo of the full-waveform Lidar carries the distance and characteristic information of the measured target. The pulse is narrow, and the full waveform recording requires a very high the sampling rate. [0003] The full-waveform LiDAR uses GHz sampling rate ADC to digitally quantize the laser main echo signal. Effective echo detection is realized after processing the full waveform data. The current RF ADC chip has high quantization bits and large data bandwidth, which is limited by the pins and operating frequency of some FPGA devices. For GHz sampling rate and high quantization bits , The digital output is an...

AI Technical Summary

Problems solved by technology

Effective echo detection is realized by processing the full waveform data. The current RF ADC chip has high quantization bits and large data bandwidth, which is limited by the pins and operating frequency of some FPGA devices. For GHz sampling rate and high quantization bits , The digital output is a parallel LVDS ADC device, the FPGA adopts the data receiving scheme of the global clock, which cannot reliably realize the data receiving, and the regional clock cannot realize the cross-bank data acquisition operation

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